Processor Design

5Z032

Arithmetic for Computers

Henk Corporaal
Eindhoven University of Technology
2011
 Topics
 Arithmetic
 Signed and unsigned numbers
 Addition and Subtraction
 Logical operations
 ALU: arithmetic and logic unit
 Multiply
 Divide
 Floating Point
 notation
 add
 multiply

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Arithmetic
 Where we've been:
 Performance (seconds, cycles, instructions)
 Abstractions:
Instruction Set Architecture
Assembly Language and Machine Language
 What's up ahead:
 Implementing the Architecture
operation

32 ALU
result

32

32
TU/e Processor Design 5Z032 3
 Binary numbers (1)
 Bits have no inherent meaning (no semantics)
 Decimal number system, e.g.:
4382 = 4x103 + 3x102 + 8x101 + 2x100
 Can use arbitrary base g; value of digit c at position i:
c x gi
 Binary numbers (base 2)
n-1 n-2 … 1 0 position

an-1 an-2 … a1 a0 digit

2n-1 2n-2 … 21 20 weight

 (an-1 an-2... a1 a0) two = an-1 x 2n-1 + an-2 x 2n-2 + … + a0 x 20

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 Binary numbers (2)
 So far numbers are unsigned
 With n bits 2n possible combinations

1 bit 2 bits 3 bits 4 bits decimal value

0 00 000 0000 0
1 01 001 0001 1
10 010 0010 2
11 011 0011 3
100 0100 4
101 0101 5
110 0110 6
111 0111 7
1000 8
1001 9

 a0 : least significant bit (lsb)

 an-1: most significant bit (msb)

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 Binary numbers (3)
 Binary numbers (base 2)
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001...
decimal: 0...2n-1

 Of course it gets more complicated:

- numbers are finite (overflow)
- fractions and real numbers
- negative numbers
 e.g., no MIPS subi instruction;
 however, addi can add a negative number

How do we represent negative numbers?

i.e., which bit patterns will represent which numbers?

TU/e Processor Design 5Z032 6

Conversion
 Decimaal -> binair
Divide by 2 Remainder
4382
2191 0
1095 1
4382ten =
547 1 1 0001 0001 1110two
273 1
136 1
68 0
34 0
17 0
8 1
4 0
2 0
1 0
0 1

 Hexadecimal: base 16. Octal: base 8

1010 1011 0011 1111two = ab3fhex

TU/e Processor Design 5Z032 7

Signed binary numbers
Possible representations:
 Sign Magnitude: One's Complement Two's Complement
000 = +0 000 = +0 000 = +0
001 = +1 001 = +1 001 = +1
010 = +2 010 = +2 010 = +2
011 = +3 011 = +3 011 = +3
100 = -0 100 = -3 100 = -4
101 = -1 101 = -2 101 = -3
110 = -2 110 = -1 110 = -2
111 = -3 111 = -0 111 = -1

 Issues: balance, number of zeros, ease of operations

 Which one is best? Why?

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Two’s complement
(let’s restrict to 4 bits)
0000
1111 0001
-1 0
1 0010
1110 15
-2 2
14
1101 -3 0011
13 3

1100 -4 12 positive
4 0100
negative
11
-5 5
1011 0101
10
-6 9 6
1010 8 0110
-7 7
-8
1001 0111
1000

TU/e Processor Design 5Z032 9

Two’s complement
0000 3+2=5
1111 0001
-1 0
1 0010
1110 15
-2 2
14
1101 -3 0011
13 3

1100 -4 12 positive
4 0100
negative
11
-5 5
1011 0101
10
-6 9 6
1010 8 0110
-7 7
-8
1001 0111
1000

TU/e Processor Design 5Z032 10

Two’s complement
3+ (-5) = -2
0000
1111 0001
-1 0
1 0010
1110 15
-2 2
14
1101 -3 0011
13 3

1100 -4 12 positive
4 0100
negative
11
-5 5
1011 0101
10
-6 9 6
1010 8 0110
-7 7
-8
1001 0111
1000

TU/e Processor Design 5Z032 11

Two’s complement
3+6 = -7 !!
0000 overflow
1111 0001
-1 0
1 0010
1110 15
-2 2
14
1101 -3 0011
13 3

1100 -4 12 positive
4 0100
negative
11
-5 5
1011 0101
10
-6 9 6
1010 8 0110
-7 7
-8
1001 0111
1000

TU/e Processor Design 5Z032 12

Two’s complement
-3 + (-6) = 7 !!
0000
underflow
1111 0001
-1 0
1 0010
1110 15
-2 2
14
1101 -3 0011
13 3

1100 -4 12 positive
4 0100
negative
11
-5 5
1011 0101
10
-6 9 6
1010 8 0110
-7 7
-8
1001 0111
1000

TU/e Processor Design 5Z032 13

Two’s complement
 32 bit signed numbers: maxint

0000 0000 0000 0000 0000 0000 0000 0000two = 0ten

0000 0000 0000 0000 0000 0000 0000 0001two = + 1ten minint
0000 0000 0000 0000 0000 0000 0000 0010two = + 2ten
...
0111 1111 1111 1111 1111 1111 1111 1110two = + 2,147,483,646ten
0111 1111 1111 1111 1111 1111 1111 1111two = + 2,147,483,647ten
1000 0000 0000 0000 0000 0000 0000 0000two = – 2,147,483,648ten
1000 0000 0000 0000 0000 0000 0000 0001two = – 2,147,483,647ten
1000 0000 0000 0000 0000 0000 0000 0010two = – 2,147,483,646ten
...
1111 1111 1111 1111 1111 1111 1111 1101two = – 3ten
1111 1111 1111 1111 1111 1111 1111 1110two = – 2ten
1111 1111 1111 1111 1111 1111 1111 1111two = – 1ten

 Range [-2 31 .. 2 31 -1]

 (an-1 an-2... a1 a0) 2’s-compl = -an-1 x 2n-1 + an-2 x 2n-2 + … + a0 x 20
= - 2n + an-1 x 2n-1 + … + a0 x 20

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Two's Complement Operations
 Negating a two's complement number: invert all bits
and add 1
 remember: “negate” and “invert” are quite different!

 Proof:
a + a = 1111.1111b = -1 d =>
-a = a + 1

TU/e Processor Design 5Z032 15

 Two's Complement Operations
Converting n bit numbers into numbers with more than n bits:
 MIPS 8 bit, 16 bit values / immediates converted to 32 bits
 Copy the most significant bit (the sign bit) into the other bits
0010 -> 0000 0010
1010 -> 1111 1010
 MIPS "sign extension" example instructions:
lb load byte (signed)
lbu load byte (unsigned)
slti set less than immediate (signed)
sltiu set less than immediate (unsigned)

TU/e Processor Design 5Z032 16

Addition & Subtraction
 Just like in grade school (carry/borrow 1s)
0111 0111 0110
+ 0110 - 0110 - 0101

 Two's complement operations easy

 subtraction using addition of negative numbers
0110 0110
- 0101 + 1010

 Overflow (result too large for finite computer word):

 e.g., adding two n-bit numbers does not yield an n-bit number
0111
+ 0001 note that overflow term is somewhat misleading,
1000 it does not mean a carry “overflowed”

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Detecting Overflow
 No overflow when adding a positive and a negative number

 No overflow when signs are the same for subtraction

 Overflow occurs when the value affects the sign:

 overflow when adding two positives yields a negative
 or, adding two negatives gives a positive
 or, subtract a negative from a positive and get a negative
 or, subtract a positive from a negative and get a positive

 Consider the operations A + B, and A – B

 Can overflow occur if B is 0 ?
 Can overflow occur if A is 0 ?

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Effects of Overflow
 When an exception (interrupt) occurs:
 Control jumps to predefined address for exception
(interrupt vector)
 Interrupted address is saved for possible resumption in
exception program counter (EPC); new instruction: mfc0
(move from coprocessor0)
 Interrupt handler handles exception (part of OS).
registers $k0 and $k1 reserved for OS

 Details based on software system / language

 C ignores integer overflow; FORTRAN not

 Don't always want to detect overflow

— new MIPS instructions: addu, addiu, subu
note: addiu and sltiu still sign-extends!
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 Logic operations
 Sometimes operations on individual bits needed:

Logic operation C operation MIPS instruction

Shift left logical << sll
Shift right logical >> srl
Bit-by-bit AND & and, andi
Bit-by-bit OR | or, ori

 and and andi can be used to turn off some bits;

or and ori turn on certain bits
 Of course, AND en OR can be used for logic operations.
 Note: Language C’s logical AND (&&) and OR (||) are conditional
 andi and ori perform no sign extension !

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Exercise: gates
Given: 3-input logic function of A, B and C, 2-outputs

Output D is true if at least 2 inputs are true

Output E is true if odd number of inputs true

 Give truth-table

 Give logic equations

 Give implementation with AND and OR gates, and

Inverters.

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An ALU (arithmetic logic unit)
 Let's build an ALU to support the andi and ori
instructions
 we'll just build a 1 bit ALU, and use 32 of them

operation

a result
b

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Review: The Multiplexor
 Selects one of the inputs to be the output, based on a
control input
S note: we call this a 2-input mux
even though it has 3 inputs!
A 0
C
B 1

 Lets build our ALU and use a MUX to select the

outcome for the chosen operation

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Different Implementations
 Not easy to decide the “best” way to build something
 Don't want too many inputs to a single gate
 Don’t want to have to go through too many gates
 For our purposes, ease of comprehension is important
 Let's look at a 1-bit ALU for addition (= full-adder):
CarryIn
cout = a b + a cin + b cin
a sum = a xor b xor cin
+ Sum
b

CarryOut

 How could we build a 1-bit ALU for add, and, and or?
 How could we build a 32-bit ALU?
TU/e Processor Design 5Z032 24
 Building a 32 bit ALU
CarryIn Operation

a0 CarryIn
Operation ALU0
Result0
b0
CarryIn CarryOut

a a1 CarryIn
0 ALU1
Result1
b1
CarryOut

1
Result
a2 CarryIn
Result2
ALU2
b2
2 CarryOut
b

CarryOut
a31 CarryIn
Result31
ALU31
b31

TU/e Processor Design 5Z032 25

What about subtraction (a – b) ?
 Two's complement approach: just negate b and add
 How do we negate?

 A very clever solution:

Binvert Operation
CarryIn

a
0

1
Result

b 0 2

CarryOut
TU/e Processor Design 5Z032 26
Tailoring the ALU to the MIPS
 Need to support the set-on-less-than instruction (slt)
 remember: slt rd,rs,rt is an arithmetic instruction
 produces a 1 if rs < rt and 0 otherwise
 use subtraction: (a-b) < 0 implies a < b

 Need to support test for equality

 beq $t5, $t6, label
 jump to label if $t5 = $t6
 use subtraction: (a-b) = 0 implies a = b

TU/e Processor Design 5Z032 27

 Binvert Operation

Supporting 'slt'
CarryIn

a
0

 Can we figure out the Result

idea? b 0 2

(fig. 4.17 2nd ed.) 1

Less 3
bits 0-30
a. CarryOut

Binvert Operation
CarryIn

a
0

Result
b 0 2

Less 3

Set

bit 31 Overflow
Overflow
detection
b.
Supporting Binvert CarryIn Operation

the ‘slt’ a0
b0
CarryIn
ALU0 Result0

operation Less
CarryOut

a1 CarryIn
b1 ALU1 Result1
0 Less
CarryOut

a2 CarryIn
b2 ALU2 Result2
0 Less
CarryOut

CarryIn

a31 CarryIn Result31

b31 ALU31 Set
0 Less Overflow

TU/e Processor Design 5Z032 29

 Test for equality
Bnegate Operation

 a-b = 0 a=b a0
b0
CarryIn
ALU0
Result0
Less
 Notice control lines: CarryOut

000 = and a1 CarryIn Result1

b1 ALU1
001 = or 0 Less
CarryOut Zero
010 = add
110 = subtract
111 = slt a2
b2
CarryIn
ALU2
Result2
0 Less
CarryOut

•Note: signal Zero is a 1 when the

result is zero!
•The Zero output is always calculated a31 CarryIn
Result31
b31 ALU31 Set
0 Less Overflow

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ALU symbol
operation

32
a
zero
32
ALU result
overflow
32
b

carry-out

TU/e Processor Design 5Z032 31

 Conclusions
 We can build an ALU to support the MIPS instruction set
 key idea: use multiplexor to select the output we want
 we can efficiently perform subtraction using two’s complement
 we can replicate a 1-bit ALU to produce a 32-bit ALU
 Important points about hardware
 all of the gates are always working
 not efficient from energy perspective !!
 the speed of a gate is affected by the number of connected outputs
it has to drive (so-called Fan-Out)
 the speed of a circuit is affected by the number of gates in series
(on the “critical path” or the “deepest level of logic”)
 Unit of measure: FO4 = inverter with Fan-Out of 4
 P4 (heavily superpipelined) has about 15 FO4 critical path

TU/e Processor Design 5Z032 32

Problem: Ripple carry adder is slow
 Is a 32-bit ALU as fast as a 1-bit ALU?
 Is there more than one way to do addition?
 Two extremes: ripple carry and sum-of-products
 How many logic layers do we need for these two extremes?

Can you see the ripple? How could you get rid of it?
c1 = b0c0 + a0c0 + a0b0
c2 = b1c1 + a1c1 + a1 b1 c2 = (..subst c1..)
c3 = b2c2 + a2c2 + a2 b2 c3 =
c4 = b3c3 + a3c3 + a3 b3 c4 =

Not feasible! Why not?

TU/e Processor Design 5Z032 33

 Carry-lookahead adder (1)
 An approach in-between our two extremes
 Motivation:
 If we didn't know the value of carry-in, what could we do?
 When would we always generate a carry? gi = ai bi
 When would we propagate the carry? pi = ai + bi

Cin

Cout = Gi + Pi Cin
Cout
TU/e Processor Design 5Z032 34
 Carry-lookahead adder (2)
 Did we get rid of the ripple?

c1 = g0 + p0c0
c2 = g1 + p1c1 c2 = g1 + p1(g0 + p0c0)
c3 = g2 + p2c2 c3 =
c4 = g3 + p3c3 c4 =

a0 Cin 4
Result0-3
 Feasible ? b0
a1
b1
a2 ALU
b2 P0
a3 G0
b3
P0 = p0.p1.p2.p3
G0= g3+(p3.g2)+(p3.p2.g1)+(p3.p2.p1.g0)
TU/e Processor Design 5Z032 35
Carry-lookahead
CarryIn

adder (3) a0
b0
a1
b1
CarryIn

ALU0
Result0--3

a2 pi
b2 P0
G0 gi
a3
b3 Carry-lookahead unit
C1
 Use principle to build ci + 1

bigger adders a4
b4
CarryIn
Result4--7
a5
 Can’t build a 16 bit adder b5
a6
ALU1
pi + 1
P1
b6
this way... (too big) a7
G1 gi + 1
b7
C2
 Could use ripple carry of 4- ci + 2

bit CLA adders a8 CarryIn

b8 Result8--11
a9
 Better: use the CLA b9 ALU2
a10 P2 pi + 2
principle again! b10
a11
G2 gi + 2
b11
C3
ci + 3

a12 CarryIn
b12 Result12--15
a13
b13 ALU3
a14 P3 pi + 3
b14 G3 gi + 3
a15 C4
b15 ci + 4

CarryOut
TU/e Processor Design 5Z032 36
Multiplication (1)
 More complicated than addition
 accomplished via shifting and addition
 More time and more area
 Let's look at 3 versions based on gradeschool
algorithm

0010 (multiplicand)
__*_1011 (multiplier)

 Negative numbers: convert and multiply

 there are better techniques, we won’t look at them now

TU/e Processor Design 5Z032 37

Multiplication (2)
Start

First implementation
Product initialized to 0 Multiplier0 = 1 1. Test Multiplier0 = 0
Multiplier0

Multiplicand 1a. Add multiplicand to product and

Shift left place the result in Product register

64 bits

Multiplier 2. Shift the Multiplicand register left 1 bit

64-bit ALU Shift right
32 bits
3. Shift the Multiplier register right 1 bit
Product
Control test
Write
64 bits
No: < 32 repetitions
32nd repetition?

Yes: 32 repetitions

Done

TU/e Processor Design 5Z032 38

Multiplication (3) Start

Second version Multiplier0 = 1 1. Test

Multiplier0
Multiplier0 = 0

1a. Add multiplicand to the left half of

the product and place the result in
the left half of the Product register
Multiplicand

32 bits
2. Shift the Product register right 1 bit

Multiplier
32-bit ALU Shift right
3. Shift the Multiplier register right 1 bit
32 bits

Shift right
Product Control test No: < 32 repetitions
Write 32nd repetition?

64 bits
Yes: 32 repetitions

Done

TU/e Processor Design 5Z032 39

Multiplication (4)
Start

Final version
Product initialized with multiplier Product0 = 1 1. Test Product0 = 0
Product0

Multiplicand
1a. Add multiplicand to the left half of
the product and place the result in
32 bits the left half of the Product register

32-bit ALU
2. Shift the Product register right 1 bit

Shift right Control

Product
Write test
No: < 32 repetitions
64 bits 32nd repetition?

Yes: 32 repetitions

Done

TU/e Processor Design 5Z032 40

Fast multiply: Booth’s Algorithm
 Exploit the fact that: 011111 = 100000 - 1
Therefore we can replace multiplier, e.g.:

0001111100 = 0010000000 - 100

 Rules:
Current Bit to the Explanation Operation
bit right
1 0 Begin 1s Subtract
multiplicand
1 1 Middle of 1s nothing

0 1 End of 1s Add
multiplicand
0 0 Middle of 0s nothing

TU/e Processor Design 5Z032 41

 Booth’s Algorithm (2)
 Booth’s algorithm works for signed 2’s complement as
well (without any modification)
 Proof: let’s multiply b * a
(ai-1 - ai ) indicates what to do: 0 : do nothing
+1: add b
-1 : subtract
31
We get b*a =  i1 i
( a
i 0
 a )  b  2 i


 30
i
b  a31  2   ai  2 
31

 i 0 

This is exactly what we need !

TU/e Processor Design 5Z032 42
Division
 Similar to multiplication: repeated subtract

 The book discusses again three versions

TU/e Processor Design 5Z032 43

Divide (1)
 Well known algorithm:

Dividend
Divisor 1000/1001010\1001 Quotient
-1000
10
101
1010
-1000
10 Remainder

TU/e Processor Design 5Z032 44

Division (2)
Start

1. Substract the Divisor register from the

Remainder register and place the
result in the Remainder register
 Implementation:
>= 0 <0
Test Remainder

2.a Shift the Quotient register 2.b Restore the original value by
to the left, setting the adding the Divisor register. Also,
rightmost bit to 1 shift a 1 into the Quotient register

Divisor
Shift right Shift Divisor Register right 1 bit
64 bits

Quotient no
64-bit ALU
Shift left 33rd repetition?
32 bits

Remainder Control test

yes
Write
64 bits
Done

TU/e Processor Design 5Z032 45

Multiply / Divide in MIPS
 MIPS provides a separate pair of 32-bit registers for
the result of a multiply and divide: Hi and Lo

mult $s2,$s3 # Hi,Lo = $s2 * $s3

div $s2,$s3 # Hi,Lo = $s2 mod $s3,
$s2 / $s3

 Copy result to general purpose register

mfhi $s1 # $s1 = Hi
mflo $s1 # $s1 = Lo

 There are also unsigned variants of mult and div:

multu and divu

TU/e Processor Design 5Z032 46

Shift instructions

 sll
 srl
 sra

 Why not ‘sla’ instruction ?

Shift: a quick way to multiply and divide with power of 2

(strength reduction). Is this always allowed?

TU/e Processor Design 5Z032 47

Floating Point (a brief look)
 We need a way to represent
 numbers with fractions, e.g., 3.1416
 very small numbers, e.g., .000000001
 very large numbers, e.g., 3.15576  109
 Representation:
 sign, exponent, significand: (–1)sign  significand  2exponent
 more bits for significand gives more accuracy
 more bits for exponent increases range
 IEEE 754 floating point standard:
 single precision : 8 bit exponent, 23 bit significand
 double precision: 11 bit exponent, 52 bit significand

TU/e Processor Design 5Z032 48

IEEE 754 floating-point standard
 Leading “1” bit of significand is implicit

 Exponent is “biased” to make sorting easier

 all 0s is smallest exponent all 1s is largest
 bias of 127 for single precision and 1023 for double precision
 summary: (–1)sign  (1significand)  2exponent – bias

 Example:
 decimal: -.75 = -3/4 = -3/22
 binary : -.11 = -1.1 x 2-1
 floating point: exponent = -1+bias = 126 = 01111110
 IEEE single precision:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 0 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0000000000

TU/e Processor Design 5Z032 49

Floating Point Complexities
 Operations more complicated: align, renormalize, ...
 In addition to overflow we can have “underflow”
 Accuracy can be a big problem
 IEEE 754 keeps two extra bits, guard and round, and additional
sticky bit (indicating if one of the remaining bits unequal zero)
 four rounding modes
 positive divided by zero yields “infinity”
 zero divide by zero yields “not a number”
 other complexities
 Implementing the standard can be tricky
 Not using the standard can be even worse
 see text for description of 80x86 and Pentium bug!
TU/e Processor Design 5Z032 50
Floating Point on MIPS
 Separate register file for floats: 32 single precision
registers; can be used as 16 doubles
 MIPS-1 floating point instruction set (pg 288/291)
 addition add.f (f =s (single) or f=d (double))
 subtraction sub.f
 multiplication mul.f
 division div.f
 comparison c.x.f where x=eq, neq, lt, le, gt or ge
 sets a bit in (implicit) condition reg. to true or false

 branch bc1t (branch if true) and bclf (branch if false)

 c1 means instruction from coprocessor one !

 load and store: lwc1, swc1

 Study examples on page 293, and 294-296

TU/e Processor Design 5Z032 51

Floating Point on MIPS
 MIPS has 32 single-precision FP registers ($f0,$f1,
…,$f31) or 16 double-precision ($f0,$f2,...)
 MIPS FP instructions:
FP add single add.s $f0,$f1,$f2 $f0 = $f1+$f2
FP substract single sub.s $f0,$f1,$f2 $f0 = $f1-$f2
FP multiply single mul.s $f0,$f1,$f2 $f0 = $f1x$f2
FP divide single div.s $f0,$f1,$f2 $f0 = $f1/$f2
FP add double add.d $f0,$f2,$f4 $f0 = $f2+$f4
FP substract double sub.d $f0,$f2,$f4 $f0 = $f2-$f4
FP multiply double mul.d $f0,$f2,$f4 $f0 = $f2x$f4
FP divide double div.d $f0,$f2,$f4 $f0 = $f2/$f4
load word coprocessor 1 lwc1 $f0,100($s1) $f0 = Memory[$s1+100]
store word coprocessor 1 swc1 $f0,100($s1) Memory[$s1+100] = $f0
branch on copr.1 true bc1t 25 if (cond) goto PC+4+100
branch on copr.1 false bc1f 25 if (!cond) goto PC+4+100
FP compare single c.lt.s $f0,$f1 cond = ($f0 < $f1)
FP compare double c.ge.d $f0,$f2 cond = ($f0 >= $f2)
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 Conversion: decimal  IEEE 754 FP
 Decimal number (base 10)
123.456 = 1x102+2x101+3x100+4x10-1+5x10-2+6x10-3
 Binary number (base 2)
101.011 = 1x22+0x21+1x20+0x2-1+1x2-2+1x2-3
 Example conversion: 5.375
 Multiply with power of 2, to get rid of fraction:
5.375 = 5.375x16 / 16 = 86 x 2-4
 Convert to binary, and normalize to 1.xxxxx
86 x 2-4 = 1010110 x 2-4 = 1.01011 x 22
 Add bias (127 for single precision) to exponent:
exponent field = 2 + 127 = 129 = 1000 0001
 IEEE single precision format (remind the leading “1” bit):
0 10000001 01011000000000000000000
sign exponent significand

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Floating point on Intel 80x86
 8087 coprocessor announced in 1980 as an
extension of the 8086
(similar 80287, 80387)
 80 bit internal precision (extended double format)
 8 entry stack architecture
 addressing modes:
 one operand = TOS
 other operand is TOS, ST(i) or in Memory
 Four types of instructions (table 4.49 page 303):
 data transfer
 arithmetic
 compare
 transcendental (tan, sin, cos, arctan, exponent, logarithm)
TU/e Processor Design 5Z032 54
Fallacies and pitfalls
 Associative law does not hold:

(x+y) + z is not always equal x + (y+z)

(see example pg 304)

TU/e Processor Design 5Z032 55

Summary
 Computer arithmetic is constrained by limited precision
 Bit patterns have no inherent meaning but standards do exist
 two’s complement
 IEEE 754 floating point

 Computer instructions determine “meaning” of the bit patterns

 Performance and accuracy are important so there are many

complexities in real machines (i.e., algorithms and
implementation).

 We are ready to move on (and implement the processor)

you may want to look back (Section 4.12 is great reading!)

TU/e Processor Design 5Z032 56

Exercises
From Chapter four (2nd ed.):

 4.1, 4.2, 4.4 - 4.8

 4.10, 4.12, 4.13
 4.14
 4.16, 4.20
 4.25
 4.36
 4.40
 4.49, 4.50

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