Input/Output Organization 1 Lecture 36

11-1
Overview

 Peripheral Devices

 Input-Output Interface

 Asynchronous Data Transfer

 Modes of Transfer

 Priority Interrupt

 Direct Memory Access

 Input-Output Processor

Computer System Architecture Chap. 11 Input-Output Organization Dept. of Info. Of Computer.

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 11-3 Asynchronous Data Transfer

 Synchronous Data Transfer
 All data transfers occur simultaneously during the occurrence of a clock
pulse
 Two units such as CPU and I/O Interface are designed independently of
each other. If the registers in the interface share a common clock with
CPU registers. The transfer between the two are said to be synchronous.

 Asynchronous Data Transfer

 Internal timing in each unit (CPU and Interface) is independent
 Each unit uses its own private clock for internal registers

 Asynchronous data transfer between two independent units requires that

control signals be transmitted between the communicating units to
indicate the time at which data is being transmitted.
» STROBE
» HANDSHAKING

Computer System Architecture Chap. 11 Input-Output Organization Dept. of Info. Of Computer.

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 Strobe : Control signal to indicate the time at which data is being transmitted
 1) Source-initiated strobe : Fig. 11-3
 2) Destination-initiated strobe : Fig. 11-4

Data bus Data bus

Source Destination Source Destination
unit Strobe unit unit Strobe unit

(a) Block diagram (a) Block diagram

Data  Valid data

Data
 Valid data

Strobe  Strobe 
(b) Timing diagram (b) Timing diagram

Fig. 11-3 Source-initiated strobe Fig. 11-4 Destination-initiated strobe

 Disadvantage of strobe method

» Destination Data
» Handshake method Data

Computer System Architecture Chap. 11 Input-Output Organization Dept. of Info. Of Computer.

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 Handshake : Agreement between two independent units

 1) Source-initiated handshake : Fig. 11-5
 2) Destination-initiated handshake : Fig. 11-6
Data bus Data bus

Source Data valid Destination Source Data valid Destination

unit unit unit unit
Data accepted Ready for data

(a) Block diagram

(a) Block diagram

Data
 Valid data

Ready for data


Data valid
Data valid

Data accepted
 Data bus
 Valid data

(b) Timing diagram

(b) Timing diagram
Source unit Destination unit
Source unit Destination unit
Place data on bus
Enable data valid. Accept data from bus Ready to accept
Enable data accepted data.
Place data on bus Enable ready for data
Enable data valid.

Disable data valid

Invalidate data on bus Disable data accepted Accept data from bus
Ready to accept data Disable data valid Disable reday for data
(initial state) Invalidate data on bus
(initial state)
(c) Sequence of events
(c) Sequence of events

Fig. 11-5 Source-initiated handshake Fig. 11-6 Destination-initiated handshake

 Timeout : If the return handshake signal does not respond within a given time
period, the unit assumes that an error has occurred.

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 Asynchronous Serial Transfer

 Synchronous transmission :
» The two unit share a common clock frequency
» Bits are transmitted continuously at the rate dictated by the clock pulses
 Asynchronous transmission :
» Binary information sent only when it is available and line remain idle otherwise
» Special bits are inserted at both ends of the character code
» Each character consists of three parts :
 1) start bit : always “0”, indicate the beginning of a character
 2) character bits : data
 3) stop bit : always “1”
 Asynchronous transmission rules :
»  When a character is not being sent, the line is kept in the 1-state
»  The initiation of a character transmission is detected from the start bit, which is
always “0”
»  The character bits always follow the start bit
»  After the last bit of the character is transmitted, a stop bit is detected when the line
returns to the 1-state for at least one bit time
   
1 1 0 0 0 1 0 1

Start Stop
Character bits
bit bit

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 Baud Rate : Data transfer rate in bits per second

» 10 character per second with 11 bit format = 110 bit per second
 UART (Universal Asynchronous Receiver Transmitter) : 8250
 UART (Universal Synchronous/Asynchronous Receiver Transmitter) : 8251

Computer System Architecture Chap. 11 Input-Output Organization Dept. of Info. Of Computer.

Input/Output Organization 7
11-7
Universal Asynchronous Receiver Transmitter
A typical asynchronous communication interface available as an IC
Transmit
Bidirectional Transmitter Shift data
data bus Bus register register
buffers

Control Transmitter Transmitter

clock
register control

Internal Bus
and clock
Chip select CS
Status Receiver Receiver CS RS Oper. Register selected
RS Timing clock
register control 0 x x None
I/O read and and clock 1 0 WR Transmitter register
RD Control 1 1 WR Control register
I/O write Receive 1 0 RD Receiver register
WR Receiver Shift data
1 1 RD Status register
register register

Transmitter Register
- Accepts a data byte(from CPU) through the data bus
- Transferred to a shift register for serial transmission
Receiver
- Receives serial information into another shift register
- Complete data byte is sent to the receiver register
Status Register Bits
- Used for I/O flags and for recording errors
Control Register Bits
- Define baud rate, no. of bits in each character, whether to generate and check parity, and no. of
stop bits
Computer System Architecture Chap. 11 Input-Output Organization Dept. of Info. Of Computer.