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Digital Systems
FLIP-FLOPs
BK
TP.HCM
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Introduction
• So far we have seen Combinational Logic
– The output(s) depends only on the current values of the input
variables
• Here we will look at Sequential Logic circuits
– The output(s) can depend on present and also past values of
the input and the output variables
• Sequential circuits exist in one of a defined number of
states at any one time
– They move "sequentially" through a defined sequence of
transitions from one state to the next
– The output variables are used to describe the state of a
sequential circuit either directly or by deriving state variables
from them

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General Digital System

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Synchronous and Asynchronous
Sequential Logic
• Synchronous
– The timing of all state transitions is controlled by a common
clock
– Changes in all variables occur simultaneously
• Asynchronous
– State transitions occur independently of any clock and normally
dependent on the timing of transitions in the input variables
– Changes in more than one output do not necessarily occur
simultaneously
• Clock
– A clock signal is a square wave of fixed frequency
– Often, transitions will occur on one of the edges of clock pulses
• i.e. the rising edge or the falling edge

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dce General flip-flop symbol and definition of its two
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possible output states

• We now introduce the concept of memory. The flip-

flop, abbreviated FF, is a key memory element.
• The outputs of a flip flop are Q and Q’
• Q is understood to be the normal output, Q’ is always
the opposite.

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NAND Gate Latch

• The NAND gate latch or simply latch is a basic
FF.
• The inputs are set and clear (reset)
• The inputs are active low, that is, the output will
change when the input is pulsed low.
• When the latch is set
Q  1 and Q  0
• When the latch is clear or reset

Q  0 and Q  1

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A NAND latch is an example of a bistable device

NAND
001
011
101
110

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Setting the NAND Flip-Flop

NAND
001
011
101
110

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Resetting the NAND Flip-Flop

NAND
001
011
101
110

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Function table of a NAND latch

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NAND Gate Latch

• Summary of the NAND latch:
– SET = RESET = 1. Normal resting state, outputs
remain in state prior to input.
– SET = 0, RESET = 1. Q will go high and remain
high even if the SET input goes high.
– SET = 1, RESET = 0. Q will go low and remain low
even if the RESET input goes high.
– SET = RESET = 0. Output is unpredictable because
the latch is being set and reset at the same time.

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Other Representations of a NAND latch

• Symbols indicate Q is set (high) when S is

low.

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Determine Q

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2019 A example of NAND latch Application

• NAND latch used to debounce a mechanical switch

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NOR Gate Latch

• The NOR latch is similar to the NAND latch
except that the Q and Q’ outputs are reversed.
• The SET and RESET inputs are active high, that
is, the output will change when the input is
pulsed high.
• In order to ensure that a FF begins operation at
a known level, a pulse may be applied to the
SET or RESET inputs when a device is powered
up.

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NOR gate latch
• (a) NOR gate latch; (b) function table; (c) simplified block
symbol.

• Determine Q for a NOR latch given the inputs below

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activate switch
The NAND FF is used to
provide a bounce free switch
so that the 1 KHz pulse can
propagate to the output
without distortion.

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Digital Pulses
• The transition from low to high on a positive
pulse is called rise time (tr).
– Rise time is measured between the 10% and 90%
points on the leading edge of the voltage waveform.
• The transition from high to low on a positive
pulse is called fall time (tf).
– Fall time is measured between the 90% and 10%
points on the trailing edge of the voltage waveform.

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Rise and Fall times

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Rise and Fall times

Signal that activates an active-low output with:

tw = 50ns, tr =15ns, and tf = 10 ns.

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Clock Signals and Clocked Flip-Flops

• Asynchronous system – outputs can change
state at any time the input(s) change.
• Synchronous system – output can change state
only at a specific time in the clock cycle.
– The clock signal is a rectangular pulse train or
square wave.
– Positive going transition (PGT) – when clock pulse
goes from 0 to 1.
– Negative going transition (NGT) – when clock pulse
goes from 1 to 0.
– Transitions are also called edges.
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Ideal Clock Signals

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Clock Signals and Clocked Flip-Flops

• Clocked FFs change state on one or the other
clock transitions. Some common characteristics:
– Clock inputs are labeled CLK, CK, or CP.
– A small triangle at the CLK input indicates that the
input is activated with a PGT.
– A bubble and a triangle indicates that the CLK input is
activated with a NGT.
– Control inputs have an effect on the output only at the
active clock transition (NGT or PGT). These are also
called synchronous control inputs.
– The control inputs get the FF outputs ready to change,
but the change is not triggered until the CLK edge.

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Clocked Flip-Flops

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Clock Signals and Clocked Flip-Flops

• Setup time (tS) is the minimum time interval before the
active CLK transition that the control input must be
kept at the proper level.
• Hold time (tH) is the time after the active CLK transition
during which the control input must kept at the proper
level.

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Clocked S-R Flip-Flop

• The SET-RESET (or SET-CLEAR) FF will change states
at the positive going or negative going clock edge.

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Clocked SR Flip-Flop
• Clocked S-R flip-flop that triggers only on negative-going
transitions.

• Simplified version of
the internal circuitry
for an edge-
triggered S-R flip-
flop.

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2019 Clocked SR Flip-Flop
• Implementation of edge-detector circuits used in edge-
triggered flip-flops: (a) PGT; (b) NGT. The duration of the
CLK* pulses is typically 2–5 ns.

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Clocked J-K Flip-Flop

• Operates like the S-R FF. J is set, K is clear.
• When J and K are both high the output is
toggled from whatever state it is in to the
opposite state.
• May be positive going or negative going clock
trigger.
• Has the ability to do everything the S-C FF
does, plus operate in toggle mode.

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Clocked JK Flip-Flop

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Edge-triggered J-K flip-flop

CLK* must be high for FF to change states. This condition only

occurs at the edge of a CLK transition.
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Problem: The waveforms below are to be applied to two

different FF’s. Draw Q for (a) positive edge-triggered (b)
negative edge-triggered.

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Problem 5-13 The waveforms below are to be applied to two different FF’s.
Draw Q for (a) positive edge-triggered (b) negative edge-triggered.

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Clocked D Flip-Flop
• One data input.
• The output changes to the value of the input at
either the positive going or negative going clock
trigger.

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2019 Edge-triggered D flip-flop
implementation from a J-K flip-flop

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Parallel transfer of binary data using D flip-flops

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D Latch (Transparent Latch)

• One data input.
• The clock has been replaced by an
enable line.
• The device is NOT edge triggered.
• The output follows the input only when
EN is high.

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D Latch
• D latch: (a) structure; (b) function table; (c) logic symbol.

EN must be high for D-Latch to change states.

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D Latch
• Waveforms showing the two modes of operation of the
transparent D latch.

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Asynchronous Inputs
• Inputs that depend on the clock are synchronous.
• Most clocked FFs have asynchronous inputs that
do not depend on the clock.
• The labels PRE and CLR are used for
asynchronous inputs.
• Active low asynchronous inputs will have a bar
over the labels and inversion bubbles.
• If the asynchronous inputs are not used they will
be tied to their inactive state.

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2019 Clocked J-K flip-flop with asynchronous inputs

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2019 Clocked J-K flip-flop with asynchronous inputs

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Flip-Flop Timing Considerations

• Important timing parameters:
– Setup and hold times
– Propagation delay: the time for a signal at the input to be
shown at the output.
– Maximum clocking frequency: highest clock frequency that
will give a reliable output.
– Clock pulse high and low times: minimum time that the clock
must be high before going low, and low before going high.
– Asynchronous active pulse width: the minimum time
PRESET or CLEAR must be held for the FF to set or clear
reliably.
– Clock transition times: maximum time for the clock
transitions, generally less than 50 ns for TTL, or 200 ns for
CMOS devices.
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2019 Flip–Flop Propagation Delays

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2019 Clock LOW and HIGH time

synchronous asynchronous

tw(L) is the minimum time that the CLK must remain low before it
goes high.
tw(H) is the minimum time that the CLK must remain high before it
goes low.

Similarly for asynchronous signals - but may have a different value

than the CLK signal.
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Potential Timing Problems in FF Circuits

• When the output of one FF is connected to the

input of another FF and both devices are
triggered by the same clock, there is a potential
timing problem.
• Propagation delay may cause unpredictable
outputs.
• The low hold time parameter of most FFs mean
this won’t normally be a problem.

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Propagation Delay in Synchronous Circuits

•The input (J2) to Q2 must

be held for tH after the
clock edge.

•This will occur only if tPHL

> tH.

•Usually, this is the case.

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Flip-Flop Synchronization
• Most systems are primarily synchronous
in operation, in that changes depend on
the clock.
• Asynchronous and synchronous
operations are often combined.
• The random nature of asynchronous
inputs can result in unpredictable results.

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Effects

• Asynchronous signal A can produce

partial pulses at X

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Edge-triggered flip-flop can Synchronize
Circuit
• The signal A has
no effect until
negative edge of
clock.

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Data Storage and Transfer

• Asynchronous transfers are controlled by PRE
and CLR inputs.
• Transferring the bits of a register
simultaneously is a parallel transfer.
• Transferring the bits of a register a bit at a time
is a serial transfer.

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Asynchronous Data Transfer Operation

• Uses PRE and CLR inputs to load data into FF

• PRE and CLR won’t be both low at the same time
A = 1, EN =1, PRE = 0, sets B = 1
A =0, EN =1, CLR = 0, sets B = 0 56
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2019 Synchronous transfer of contents of register X into
register Y

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Serial Data Transfer: Shift Registers

• When FFs are arranged as a shift register, bits
will shift with each clock pulse.
• FFs used as shift registers must have very low
hold time parameters to perform predictably.
Modern FFs have tH values well within what is
required.
• The direction of data shifts will depend on the
circuit requirements and the design.

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Serial Data Transfer: Shift Registers
• Parallel transfers – register contents are
transferred simultaneously with a single clock
cycle.
• Serial transfers – register contents are
transferred one bit at a time, with a clock pulse
for each bit.
• Serial transfers are slower, but the circuitry is
simpler. Parallel transfers are faster, but
circuitry is more complex.
• Serial and parallel are often combined to exploit
the benefits of each.

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Four-bit Shift Register

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2019 Serial transfer from X register into Y register

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Frequency Division and Counting

• FFs are often used to divide a frequency as
illustrated in next slide. Here the output
frequency is 1/8th the input (clock) frequency.
• The same circuit is also acting as a binary
counter. The outputs will count from 0002 to
1112
• The number of states possible in a counter is
the modulus or MOD number. Next slide is a
MOD-8 (23) counter. If another FF is added it
would become a MOD-16 (24) counter.

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MOD-8 Asynchronous Counter

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State Table & Diagram of MOD-8 Asynchronous Counter

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Microcomputer Application
• Microprocessor units (MPUs) which will be
studied later, perform many functions that
involve the use of registers for data transfer and
storage.
• MPUs may send data to external registers for
many purposes, including:
– Solenoid or relay control
– Motor starting
– Device positioning
– Motor speed controls

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Example of Microprocessor Interfacing

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Schmitt-Trigger Devices
• Not a FF but shows a memory characteristic
• Accepts slow changing signals and produces a
signal that transitions quickly.
• A Schmitt trigger device will not respond to an
input until it exceeds the positive or negative
going threshold.
• There is a separation between the two
threshold levels. This means that the device
will “remember” the last threshold exceeded
until the input goes to the opposite threshold.

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Schmitt-Trigger Response (two thresholds)

Standard inverter response to slow noisy input, and

(b) Schmitt-trigger response to slow noisy input. Often used with noisy signals

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Schmitt-Trigger Response (two thresholds)

Standard inverter response to slow noisy input, and

Often used with noisy signals
(b) Schmitt-trigger response to slow noisy input.
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One-shot (Monostable Multivibrator)

• Changes from stable state to quasi-stable state
for a period of time determined by external
components (usually resistors and capacitors).
• Nonretriggerable devices will trigger and return
to stable state.
• Retriggerable devices can be triggered while in
the quasi-stable state to begin another pulse.
• One shots are called monostable multivibrators
because they have only one stable state.
• They are prone to triggering by noise so, tend to
be used in simple timing applications.

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One-shot

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Retriggerable and Nonretriggerable Operation

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2019 Logic symbols for the 74121 nonretriggerable
one-shot

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Clock Generator Circuits

• FFs have two stable states, so are considered
bistable multivibrators.
• One shots have one stable state and are
considered monostable multivibrators.
• Astable or free-running multivibrators switch back
and forth between two unstable states. This makes
it useful for generating clock signals for
synchronous circuits.
• Crystal control may be used if a very stable clock is
needed. Crystal control is used in microprocessor
based systems and microcomputers where
accurate timing intervals are essential.

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Clock Generator Circuit: Schmitt-trigger Oscillator

Schmitt-trigger oscillator using a 7414 INVERTER. A 7413

Schmitt-trigger NAND may also be used.

Circuit will not oscillate if R is not kept within these limits.

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2019 Clock Generator Circuit: 555 Timer
555 timer IC used astable multivibrator.

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Problem:Determine the Q output

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The signals A and B are applied to the inputs of an SR flip-

flop (or Set-Clear FF), a transparent latch and a D-type flip-
flop. Sketch the waveforms at W, X, Y and Z.

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The circuit below is made from two D-type flip-flops with an

asynchronous RESET input. Assume that Q0 and Q1 are
both low initially and sketch a timing diagram showing the
waveforms of CLOCK, Q0 and Q1 for the next six clock
pulses.

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2019 For the following circuit, complete the timing diagram below
(for A, B, and z).
PRE'

z
x D A J B

A' K B'

CLOCK

CLR'

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