Lecture 17

OUTLINE
• The MOS Capacitor (cont’d)
– Small-signal capacitance
(C-V characteristics)

Reading: Pierret 16.4; Hu 5.6

 MOS Capacitance Measurement
• VG is scanned slowly
C-V Meter MOS Capacitor • Capacitive current due
to vac is measured
dvac
iac
GATE iac  C
dt
vac
Semiconductor dQGATE dQs
C 
dVG dVG

EE130/230A Fall 2013 Lecture 17, Slide 2

 MOS C-V Characteristics
(p-type Si)
accumulation depletion inversion

dQs
VFB VT
VG
C
dVG
Qinv
C
slope = -Cox Cox

Ideal C-V curve:

VG
VFB VT
accumulation depletion inversion

EE130/230A Fall 2013 Lecture 17, Slide 3

 Capacitance in Accumulation
(p-type Si)
• As the gate voltage is varied, incremental charge is added (or
subtracted) to (or from) the gate and substrate.
 The incremental charges are separated by the gate oxide.
M O S
DQ

Q
dQacc
C  Cox
-Q dVG
DQ

Cox

EE130/230A Fall 2013 Lecture 17, Slide 4

 Flat-Band Capacitance
(p-type Si)
• At the flat-band condition, variations in VG give rise to the
addition/subtraction of incremental charge in the substrate,
at a depth LD
– LD is the “extrinsic Debye Length,” a characteristic screening distance,
or the distance where the electric field emanating from a perturbing
charge falls off by a factor of 1/e

 Si kT
LD 
q2 N A
1 1 LD
 
Cox CDebye
CFB Cox  Si

EE130/230A Fall 2013 Lecture 17, Slide 5

 Capacitance in Depletion
(p-type Si)
• As the gate voltage is varied, the depletion width varies.
 Incremental charge is effectively added/subtracted at a
depth W in the substrate.

M O S
DQ dQdep 1 2(VG  VFB )
C  
Q W dVG Cox
2
qN A Si
DQ
-Q
1 1 1 1 W
   
C Cox Cdep Cox  Si
Cox Cdep

EE130/230A Fall 2013 Lecture 17, Slide 6

 Capacitance in Inversion
(p-type Si)
CASE 1: Inversion-layer charge can be supplied/removed
quickly enough to respond to changes in gate voltage.
 Incremental charge is effectively added/subtracted at the
surface of the substrate.
DQ
M O S Time required to build inversion-layer
WT charge = 2NAto/ni , where
to = minority-carrier lifetime at surface

DQ dQinv
C  Cox
dVG
Cox

EE130/230A Fall 2013 Lecture 17, Slide 7

 Capacitance in Inversion
(p-type Si)
CASE 2: Inversion-layer charge cannot be supplied/removed
quickly enough to respond to changes in gate voltage.
 Incremental charge is effectively added/subtracted at a
depth WT in the substrate.
DQ 1 1 1
 
M O S C Cox Cdep
WT
1 WT
DQ  
Cox  Si
1 2(2F ) 1
  
Cox Cdep Cox qN A Si C min

EE130/230A Fall 2013 Lecture 17, Slide 8

 Supply of Substrate Charge
(p-type Si)
Accumulation: Depletion:

Inversion: Case 1 Case 2

C. C. Hu, Modern Semiconductor Devices for ICs, Figure 5-17

EE130/230A Fall 2013 Lecture 17, Slide 9
MOS Capacitor vs. MOS Transistor C-V
(p-type Si)
C MOS transistor at any f,
MOS capacitor at low f, or
quasi-static C-V
Cmax=Cox
CFB

MOS capacitor at high f

Cmin
VG
accumulation depletion inversion
VFB VT

EE130/230A Fall 2013 Lecture 17, Slide 10

 Quasi-Static C-V Measurement
(p-type Si)
C

Cmax=Cox
CFB

Cmin
VG
accumulation depletion inversion
VFB VT
The quasi-static C-V characteristic is obtained by slowly ramping the
gate voltage (< 0.1V/s), while measuring the gate current IG with a
very sensitive DC ammeter. C is calculated from IG = C·(dVG/dt)
EE130/230A Fall 2013 Lecture 17, Slide 11
 Deep Depletion
(p-type Si)
• If VG is scanned quickly, Qinv cannot respond to the change in
VG. Then the increase in substrate charge density Qs must
come from an increase in depletion charge density Qdep
 depletion depth W increases as VG increases
 C decreases as VG increases

C
Cox

Cmin
VG
VFB VT

EE130/230A Fall 2013 Lecture 17, Slide 12

MOS C-V Characteristic for n-type Si

MOS transistor at any f, C

MOS capacitor at low f, or
quasi-static C-V
Cmax=Cox
CFB

MOS capacitor at high f

Cmin
VG
accumulation depletion inversion
VT VFB

EE130/230A Fall 2013 Lecture 17, Slide 13

 Examples: C-V Characteristics
C
QS
Cox

HF-Capacitor
VG
VFB VT

Does the QS or the HF-capacitor C-V characteristic apply?

(1) MOS capacitor, f=10kHz
(2) MOS transistor, f=1MHz
(3) MOS capacitor, slow VG ramp
(4) MOS transistor, slow VG ramp

EE130/230A Fall 2013 Lecture 17, Slide 14

 Example: Effect of Doping
• How would the normalized C-V characteristic below change if
the substrate doping NA were increased?
– VFB
– VT
– Cmin

C/Cox
1

VFB VT

EE130/230A Fall 2013 Lecture 17, Slide 15

Example: Effect of Oxide Thickness
• How would the normalized C-V characteristic below change if
the oxide thickness xo were decreased?
– VFB
– VT
– Cmin

C/Cox
1

VFB VT

EE130/230A Fall 2013 Lecture 17, Slide 16

Derivation of Time to Build Inversion-Layer Charge
(for an NMOS device, i.e. p-type Si)
D D i  pn
2
n p n
The net rate of carrier generation is:  
(ref. Lecture 5, Slide 24) t t t p (n  n1 )  t n ( p  p1 )
( ET  Ei ) / kT ( Ei  ET ) / kT
n
where 1  ni e  ni and p1  ni e  ni
since trap states that contribute most significantly to G-R have an associated
energy level near the middle of the band gap.
Dn Dp ni
Within the depletion region, n and p are negligible, so  
where tn  tp  to t t 2t o

Therefore, the rate at which the inversion-layer charge density Qinv (units: C/cm2)
increases due to thermal generation within the depletion region (of width W) is
dQinv ni
 q W
dt 2t o

EE130/230A Fall 2013 Lecture 17, Slide 17

For a fixed value of gate voltage, the total charge in the semiconductor is fixed:

QS  Qinv  Qdep  constant

dQinv dQdep d  qN AW 
Therefore  
dt dt dt
qni dW
  W  qN A
2t o dt
dW ni
  W 0
dt 2 N At o

The solution to this differential equation is W  e  ni / 2 N At o t  e  t /t

2 N At o
where t
ni

EE130/230A Fall 2013 Lecture 17, Slide 18