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Interrupts

Interrupts allow external events to interrupt normal program execution. There are several types of interrupts including program errors, timers, I/O devices, and hardware failures. When an interrupt occurs, the processor suspends the current program, saves its context, and executes an interrupt handler routine before restoring context and resuming the original program. Multiple interrupts can be handled by disabling other interrupts or assigning priorities so higher priority interrupts can preempt lower ones.

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438 views

Interrupts

Interrupts allow external events to interrupt normal program execution. There are several types of interrupts including program errors, timers, I/O devices, and hardware failures. When an interrupt occurs, the processor suspends the current program, saves its context, and executes an interrupt handler routine before restoring context and resuming the original program. Multiple interrupts can be handled by disabling other interrupts or assigning priorities so higher priority interrupts can preempt lower ones.

Uploaded by

Vijay Pandey
Copyright
© © All Rights Reserved
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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Interrupts

• A signal informing a program that an event has occurred.


• All computers provide a mechanism by which other modules may
interrupt the normal processing of CPU.
• List of common classes of interrupts are :
1. Program: Generated by some condition that occurs
because of an instruction execution. E.g. arithmetic
overflow, division by zero, reference outside a user’s
allowed memory space.
2. Timer: Generated by timer within the processor.
3. I/O: Generated by I/O controller
4. Hardware failure: Generated by a failure such as power
failure or memory parity error.
• Interrupts are provided primarily to improve processing
efficiency.
• From the point of view of user program, an interrupt is just an
interruption of normal sequence of execution.
• If the CPU is idle, interrupt is served.
• When interrupt processing is completed, execution resumes.
• The processor and the operating system are responsible for
suspending the user program and then resuming it at the same
point.
Interrupt Cycle

• Added to instruction cycle


• Processor checks for interrupt
─ Indicated by presence of an interrupt signal
• If no interrupt, fetch next instruction
• If interrupt pending:
─ Suspend execution of current program.
─ Save context. i.e. save the address of next instruction
to be executed (in current program) and any other data
relevant to processor’s current activity.
─ Set PC to start address of interrupt handler routine
─ Process interrupt
─ Restore context and continue interrupted program
Multiple interrupts
• How to handle multiple (more than one) interrupt.
• E.g. if a program receives data from a communication line
and prints the result. The printer will generate interrupt
every time it completes a print operation. The
communication line controller will generate interrupt every
time a unit of data arrives.
• Here it is possible for a communication interrupt to occur
while a printer interrupt is being processed.
• There are 2 ways to handle them.
• Disable interrupts
– Disable the interrupt while an interrupt is being processed
– Disabled interrupts means processor can & will ignore
that interrupt
– If interrupts occur during this time, they remain pending
and are checked after processor has enabled interrupt.
– Interrupts are handled in sequence as they occur

• Define priorities
– Low priority interrupts can be interrupted by higher
priority interrupts
– When higher priority interrupt has been processed,
processor returns to previous interrupt

• Multiple interrupts can be sequential or nested.


Example of multiple interrupts (considering priorities):
We have a system with 3 I/O devices: a printer, a disk, and a
communication line, with priorities of 2, 4, 5 respectively.
At t=0, user program begins.
At t=10, a printer interrupt occurs
At t=15, a communications interrupt occurs
At t=25, a disk interrupt occurs
Transfer of control occurs in a manner as shown in next figure.

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