Chapter 3

Addressing Modes
Barry B. Brey
[email protected]

Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
 Addressing Modes
 In order to write a program addressing modes
must be thoroughly understood.
 There are many addressing modes, but the most
common are easy to master and represent most
instructions in most programs.
 Register addressing, immediate addressing,
direct addressing, and simple forms of indirect
addressing are the most common addressing
modes.

Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
  Stack addressing is also used with the
PUSH and POP instructions and as a way
to link a program to its procedures or
functions.
 Program flow instructions are either
unconditional or conditional.
 Conditional program flow instructions are
the “if” statements of assembly language.

Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
 Data Addressing Modes
 Data addressing modes are presents with
the MOV instruction because it is by far
the most common instruction in a program.
 MOV really moves nothing. MOV copies
the source into the destination. It probably
should be named COP for copy, but it is
not.

Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
 Register
 MOV EAX,EBX
 MOV CX,DX
 MOV AH,AL
 MOV AX,DS
 MOV ES,CX
 ADD AL,CL (most instructions use it)
 OR AX,DX

Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
 Immediate
 MOV EAX,234H
 MOV CX,2
 MOV AL,34H
 ADD AL,3
 SUB CL,4
 AND EAX,1

Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
 Direct
 MOV BOB,EAX
 MOV FRED,CX
 MOV BILLY,AL
 MOV EDI,RALPH
 MOV AX,STEVE
 MOV DS,BARNEY
 MOV AL,DS:[1000H]

Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
 Register Indirect
 MOV AL,[BX]
 MOV AX[EBX]
 MOV [EDI],EAX
 MOV [EAX],EDX
 MOV BYTE PTR [EAX],6
 MOV WORD PTR [ECX],12
 MOV DWORD PTR [ESI],2345H

Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
 Base Plus Index
 MOV AL,[BX+SI]
 MOV [BX+DI],AX
 MOV [BP+SI],EAX
 MOV AL,[BP+DI]
 MOV WORD PTR [BX+SI],5
 ADD AL,[BX+DI]

Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
 Register Relative
 MOV AL,[BX+3]
 MOV AX,[DI+20H]
 MOV [EDI+200H],EAX
 MOV [BX-33],ECX
 ADD BYTE PTR [BX+2],5

Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
 Relative Plus Index
 MOV AL,[BX+SI+22]
 MOV [BX+DI-22],AX
 MOV EAX,[EBX+EDI+100H]

Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
 Scaled Index
 MOV EAX,[EBX+ 4*ECX]
 MOV AX,[EDI+2*EBX]
 MOV [EAX+2*EBX],DX
 MOV [4*ECX],EBX
 ADD AL,[ECX+EBX]

Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
 Program Flow
 Program flow instruction are unconditional
(JMP) or conditional (JNZ).
 Flow instructions are short (+127, -128),
near (±32K), or far (anywhere in the
memory).
 Conditionals do not contain the far type.
 Labels are followed by a colon if they are
jumped to in a program.

Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
 Stack Addressing
 The SS (stack segment) and the SP/ESP are
added to form an address in the stack.
 The stack is an area of memory that functions as
a last-in, first-out (LIFO) memory. That is if a 1
followed by a 2 are placed on the stack the 2
comes out of the stack first, followed by the 1.
 PUSH and POP are used to store data on the
stack and to remove data from the stack as
words or doubleword,

Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
  PUSH AX
 PUSH EAX
 POP AX
 POP EAX
 PUSH BOB
 POP BOB
 PUSHF
 POPF

Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.