Module 2

Logical Effort calculation:

We will use a standard-cell library for a 3.3 V, 0.5 m m (0.6 m m
drawn) technology (from Compass) to illustrate our model, We call
this technology C5 (SPICE MODEL)
The equation for the delay of a 1X drive, two-inputNAND cell is in
the form of
( C out is in pF):
t PD = (0.07 + 1.46 C out + 0.15) ns
(S=1, R=1.5K,tq=0.15ns)

the delay equation for a 2X drive ( s = 2), two-input NAND cell is

t PD = (0.03 + 0.75 C out + 0.51) ns
Logical Paths:
• So far we have only considered a single-stage logic cell, but we can
extend the idea of logical effort to a chain of logic cells or logical path .
• Consider the logic path when we use a minimum-size inverter ( g 0 = 1,
p 0 = 1, q 0 = 1.7) to drive one input of a 2X drive, three-input NOR logic
cell with
g 1 = ( nr + 1)/( r + 1), p 1 = 3, q 1 =3,
and a load equal to four standard loads.
If the logic ratio is r = 1.5, then g 1 = 5.5/2.5 = 2.2.
• The delay of the inverter is
d = g 0 h 0 + p 0 + q 0 = (1) · (2g 1 ) · (C inv /C inv ) +1 + 1.7
= (1)(2)(2.2) + 1 + 1.7
= 7.1
Optimum Delay
• To optimize delay in a logic path,
• The path logical effort G is the product of logical efforts on a path:

• The path electrical effort H is the product of the electrical efforts

on the path,
Optimum Number of Stages

•  Chain of N inverters each with equal stage effort, f=gh

• Total path delay is Nf=Ngh=Nh, since g=1 for an inverter
• To drive a path electrical effort H, =H, or Nlnh=lnH
• Delay, Nh = h lnH/lnh
• Since lnH is fixed, we can only vary h/ln(h)
• h/ln(h) is a shallow function with a minimum at h=e»2.718
• Total delay is Ne=elnH
 Library-Cell Design
• The optimum cell layout for each process generation changes
because the design rules for each ASIC vendor’s process are always
slightly different even for the same generation of technology.
• We would like all vendors to agree on a common set of design
rules.
• The reason that most vendors have similar rules is because most
vendors use the same manufacturing equipment and a similar
process.
• It is possible to construct a highest common denominator library that
extracts the most from the current manufacturing capability.
• Layout of library cells is either hand-crafted or uses some form
of symbolic layout (stick/log, graphics)
PROGRAMMABLE ASIC LOGIC
CELLS
• All programmable ASICs or FPGAs contain a basic logic
cell replicated in a regular array across the chip (analogous
to a base cell in an MGA).
• There are the following three different types of basic logic
cells:
1. Multiplexer based,
2. Look-up table based, and
3. Programmable array logic.
The choice among these depends on the programming
technology.
ACTEL ACT:
The basic logic cells in the Actel ACT family of FPGAs are called Logic Modules 

• ACT 1 Logic Module

Shannon’s expansion theorem
• Shannon expansion theorem to expand F =A·F(A='1') +
A'·F(A='0')
• Example:
F =A'·B + A·B·C' + A'·B'·C
= A·(B·C') + A'·(B + B'·C)
F(A='1')=B·C' is the cofactor of F with respect to (wrt) A or FA
If we expand F wrt B,
F =A'·B + A·B·C' + A'·B'·C
= B·(A' + A·C') + B'·(A'·C)
Eventually we reach the unique canonical form, which uses only minterms
(A minterm is a product term that contains all the variables of F—such as
A·B'·C)
 F=(A·B) + (B'·C) + D
Expand F wrt B:
F=B·(A + D) + B'·(C + D) =B·F2 + B'·F1,
F = 2:1 MUX, with B selecting between two inputs:
F(A='1') and F(A='0')
F also describes the output of the ACT 1 LM
Now we need to split up F1 and F2
Expand F2 wrt A, and F1 wrt C:
F2=A + D=(A·1) + (A'·D);
F1=C + D=(C·1) + (C'·D)
A, B, C connect to the select lines and '1' and D are the inputs of the
MUXes in the ACT 1 LM Connections:
A0=D, A1='1', B0=D, B1='1', SA=C, SB=A, S0='0', and S1=B
Multiplexer Logic as Function Generators
The 16 logic functions of 2 variables:
• 2 of the 16 functions are not very interesting (F='0', and F='1')
• There are 10 functions that we can implement using just one 2:1MUX
• 6 functions are useful: INV, BUF, AND, OR, AND1-1, NOR1-1
Example of using the WHEEL functions to implement
F=NAND(A, B)=(A·B)'
1. First express F as the output of a 2:1 MUX:
we do this by expanding F wrt A
(or wrt B; since F is symmetric)
F=A·(B') + A'·('1')
2. Assign WHEEL1 to implement INV(B),
and WHEEL2 to implement '1'
3. Set the select input to the
MUX connecting WHEEL1 and WHEEL2, S0+S1=A.
We can do this using S0=A, S1='1'
Actel 2 and Actel 3 LM
• ACT 1 requires 2 LMs per flip-flop: with unknown interconnect
capacitance
• ACT 2 and ACT 3 use two types of LMs, one includes a D flip-flop
• ACT 2 C-Module is similar to the ACT 1 LM but can implement five-
input logic functions
• combinatorial module implements combinational logic
• ACT 2 S-Module (sequential module) contains a C-Module and a
sequential element
Timing in Actel
CLK1:
tSUD=t'SUD + (t'PD – t'CLKD),
tH=t'H + (t'PD – t'CLKD),
tCO=t'CO + t'CLKD

Speed Grading
• Speed grading (or speed binning)
uses a binning circuit
• Measure tPD=(tPLH + tPHL)/2
use the fact that properties match across a chip
Actel speed grades are based on 'Std' speed grade
Xilinx LCA (Logic cell Array)
• Uses configurable logic block,
• Coarse grain architecture
XC3000 CLB A 32-bit look-up table (LUT)
CLB propagation delay is fixed, independent
of the logic function
7 inputs : 5 CLB inputs (A–E), and 2 flip-flop
outputs (QX and QY)
2 outputs from the LUT (F and G). Since a 32-
bit LUT requires only five variables to Use 5 of
the 7 possible inputs (A–E, QX, QY) with the
entire 32-bit LUT
• Split the 32-bit LUT in half to implement 2
functions of 4 variables each;
• choose 4 input variables from the 7 inputs
(A–E, QX, QY).
• You have to choose 2 of the inputs from the
5 CLB inputs (A–E); then one function output
connects to F and the other output connects
to G.
You can split the 32-bit LUT in half, using one
of the 7 input variables as a select input to a
XC4000 CLB • This is a fairly complicated basic
logic cell containing 2 four-input
LUTs that feed a three-input LUT.
• The XC4000 CLB also has special
fast carry logic hard-wired
between CLBs.
• MUX control logic maps four
control inputs (C1–C4) into the
four inputs: LUT input H1, direct
in (DIN), enable clock (EC), and a
set / reset control (S/R) for the
flip-flops.
• The control inputs (C1–C4) can
also be used to control the use
of the F' and G' LUTs as 32 bits
of SRAM.
XC5200 Logic Block • A Logic Cell or LC, used in the
XC5200 family of Xilinx LCA
FPGAs. 
• The LC is similar to the CLBs in
the XC2000/3000/4000 CLBs,
but simpler.
• The XC5200 LC contains a four-
input LUT, a flip-flop, and MUXes
to handle signal switching.
• The arithmetic carry logic is
separate from the LUTs.
• A limited capability to cascade
functions is providedto gang two
LCs in parallel to provide the
equivalent of a five-input LUT.
Altera Flex
• Altera uses in its
FLEX 8000 series of
FPGAs.
• The FLEX cell resembles
the XC5200 LC
architecture.
• The FLEX LE uses a four-
input LUT, a flip-flop,
cascade logic, and carry
logic.
• Eight LEs are stacked to
form a Logic Array Block.
Altera Max
Logic Expanders
F = A' · C · D + B' · C · D + A · B + B · C'.
This function has four product terms
and thus we cannot implement F
using a macrocell that has only a
three-wide OR array.

If we rewrite F as a “sum of (products of products)” like this:

• F = (A' + B') · C · D + (A + C') · B
• = (A · B)' (C · D) + (A' · C)' · B
Altera Max Architecture
MODULE 3
LOW-LEVEL DESIGN ENTRY
• The purpose of design entry is to describe a microelectronic system to a set
of electronic-design automation ( EDA ) tools.
• Design entry for these systems now usually consists of drawing a picture, a schematic .
• The schematic shows how all the components are connected together,
the connectivity of an ASIC. (schematic entry , or schematic capture) 
• A circuit schematic describes an ASIC in the same way an architect’s plan describes a
building.
• The circuit schematic is a picture, an easy format for us to understand and use, but
computers need to work with an ASCII or binary version of the schematic that we call
a netlist .
• Not all the design information may be conveyed in a circuit schematic or netlist, because
not all of the functions of an ASIC are described by the connectivity information.
• Alternative design-entry methods can use graphical methods, such as a schematic, or
text files, such as a programming language. Using a hardware description
language ( HDL ) for design entry allows us to generate netlists directly using logic
synthesis .
Schematic Entry
• Schematic entry is the most common method of design entry for ASICs and is
likely to be useful in one form or another for some time.
• HDLs are replacing conventional gate-level schematic entry, but new graphical
tools based on schematic entry are now being used to create large amounts of
HDL code.

Terms used in circuit schematics

• Circuit schematics are drawn on schematic sheets .
• Standard schematic sheet sizes are ANSI A–E (more common in the United
States) and ISO A4–A0 (more common in Europe).
• Usually a frame or border is drawn around the schematic containing boxes
that list the name and number of the schematic page, the designer, the
date of the drawing, and a list of any modifications or changes.
• Schematic-entry tools for ASIC design are similar to those for printed-
circuit board (PCB) design.
• The basic object on a PCB schematic is a component or device —a TTL
IC or resistor.
• We can normally draw every component on a few schematic sheets for
a PCB, but drawing every component on an ASIC schematic is
impractical.

 IEEE-recommended dimensions and their construction for logic-gate symbols.

(a) NAND gate (b) exclusive-OR gate (an OR gate is a subset).
Hierarchical Design

• Hierarchy reduces the
size and complexity of a
schematic.
The Cell Library
• Components in an ASIC schematic are chosen from a library of cells.
• Library elements for all types of ASICs are sometimes also known
as modules .
• Most ASIC companies provide a schematic library of primitive gates to be
used for schematic entry.
• The first problem with ASIC schematic libraries is that there are no naming
conventions. For example, a primitive two-input NAND gate in a Xilinx FPGA
library does not have the same name as the two-input NAND gate in an LSI
Logic gate-array library.
• A second problem with ASIC schematic libraries is that there are no standards
for cell behavior. (porting a design)
• There are two types of macros for MGAs and programmable ASICs.
• The most common type of macro is a hard macro that includes
placement information.
• A hard macro can change in position and orientation, but the relative
location of the transistors, other layout, and wiring inside the macro is
fixed.
• A soft macro contains only connection information (between transistors
for a gate array or between logic cells for a programmable ASIC).
• Thus the placement and wiring for a soft macro can vary. This means
that the timing parameters for a soft macro can only be determined
after you complete the place-and-route step.
• A standard cell contains layout information on all mask levels.
• An MGA hard macro contains layout information on just the metal,
contact, and via layers.
Names

• Each of the cells, primitive or not, that you place on an ASIC

schematic has a cell name .
• Each use of a cell is a different instance of that cell, and we give each
instance a unique instance name .
• A cell instance is somewhere between a copy and a reference to a cell
in a library.
• An analogy would be the pictures of hamburgers on the wall in a fast-
food restaurant.
• The pictures are somewhere between a copy and a reference to a
real hamburger.
• We represent each cell instance by a picture or icon , also known as
a symbol .
• We can represent primitive cells, such as NAND and NOR gates, with
familiar icons that look like spades and shovels.
• Some schematic editors offer the option of switching between these
familiar icons and using the rectangular IEEE standard symbols for
logic gates.
• There is no accepted way to differentiate between an icon that
represents a primitive cell and one that represents a subschematic
that may be in turn a collection of primitive cells.
• In fact, there is usually no easy way to tell by looking at a schematic
which icons represent primitive cells and which represent
subschematics.
Schematic Icons and Symbols
• Most schematic-entry programs allow the designer to draw special or
custom icons.
• In addition, the schematic-entry tool will also usually create an icon
automatically for a subschematic that is used in a higher-level
schematic.
• This is a derived icon , or derived symbol . The external connections of
the subschematic are automatically attached to the icon, usually a
rectangle.
 Nets
•  local nets and external nets.
• The usual convention for naming nets in a hierarchical schematic uses
the parent cell instance name as a prefix to the local net name.
• A special character ( ':' '/' '$' '#' for example) that is not allowed to
appear in names is used as a delimiter to separate the net name from
the cell instance name.
• Input, output, signals(wire or reg).
Schematic Entry for ASICs and
PCBs
• A symbol on a schematic may represent a component, which may
contain component parts.
• A component is slightly different from an ASIC library cell.
• A simple example of a component would be a TTL gate, an SN74LS00N, that
contains four 2-input NAND gates. We call an SN74LS00N a component and each
of the individual NAND gates inside is a component part.
• Another common example of a component would be a resistor pack—a single
package that contains several identical resistors.
• In PCB design language a component label or name is a reference designator .
• A reference designator is a unique name attribute, such as R99 , attached to each
component. A reference designator, such as R99 , has two pieces: an alpha
prefix R and a numerical suffix 99 . To understand the difference between
reference designators and instance names, we need to look at the special
requirements of PCB design.
• PCBs usually contain packaged ASICs and other ICs that have pins that are
soldered to a board.
• For rectangular, dual-in-line (DIP) packages the pins are numbered
counterclockwise from the upper-left corner looking down on the package.
• IC symbols have a pin number for each part in the package.
• The number of wire crossings on a PCB is minimized by careful assignment of
components to packages and choice of parts within a package. 
• There is no process in ASIC design directly equivalent to the process of part
assignment described above and thus no need to use reference designators.
• The reference-designator naming convention quickly becomes unwieldy if
there are a large number of components in a design.
• In large hierarchical ASIC designs it is difficult to provide a unique reference
designator to each element.
• For this reason ASIC designs use instance names to identify the individual
components. Meaningful namecan be assigned to low-level components.
Connections
• Cell instances have terminals that are the inputs and outputs of the cell.
Terminals are also known as pins , connectors , or signals .
• Electrical connections between cell instances use wire segments or nets .
• We can group closely related nets, such as the 32 bits of a 32-bit digital
word, together into a bus or into buses (not busses).
• If signals on a bus are not closely related, we usually use the
term bundle or array instead of bus.
Vectored Instances and Buses
• The buses are labeled with the appropriate bits. 
Edit-in-Place
• Using edit-in-place we can edit the cell Floor .
• Suppose we change some of the cell instances of cell
name NoWindowOffice to instances of cell name WindowOffice .
• When we finish editing and save the cell Floor , we have effectively changed
all of the floors that contain instances of this cell.
• Instead of editing a cell in place, you may really want to edit just one
instance of a cell and leave any other instances unchanged.
• In this case you must create a new cell with a new symbol and new, unique
cell name.
• It might also be wise to change the instance name of the new cell to avoid
any confusion.
Attributes
• You can attach a name , also known as an identifier or label , to a component, cell
instance, net, terminal, or connector.
• You can also attach an attribute , or property , which describes some aspect of
the component, cell instance, net, or connector.
• Each attribute has a name, and some attributes also have values.
• The most common problems in working with schematics and netlists, especially
when you try to exchange schematic information between different tools, are
problems in naming.
• Since cells and their contents have to be stored in a database, a cell name
frequently corresponds (or is mapped to) a filename.
• This then raises the problems of naming conventions including: case sensitivity,
name-collision resolution, dictionaries, handling of “common” special
characters ,other special characters (such as characters in foreign alphabets), first-
character restrictions, name-length problems and so on.
Netlist Screener
• A surprising number of problems can be found by checking a schematic for
obviously fatal errors.
• A program that analyzes a schematic netlist for simple errors is sometimes
called a schematic screener or netlist screener .
• Errors that can be found by a netlist screener include:
1. unconnected cell inputs,
2. unconnected cell outputs,
3. nets not driven by any cells,
4. too many nets driven by one cell,
5. nets driven by more than one cell.
• The screener can work continuously as the designer is creating the schematic
or can be run as a separate program independently from schematic entry.
• Usually the designer provides attributes that give the screener the information
necessary to perform the checks.
• A screener usually generates a list of errors together with the locations of
the problem on the schematic where appropriate.
• Some editors associate an identifier, or handle , to every piece of a
schematic, including comments and every net.
• Normally there is some convention to the assigned names such as a grid on
a schematic.
• This works like the locator codes on a map, so that a net with A1 as part of
the name is in the upper-left-hand corner,
• for example. This allows you to quickly and uniquely find any problems
found by a screener.
• The term handle is a computer programming term that is used in referring
to a location in memory.
• Each piece of information on a schematic is stored in lists in memory. This
technique breaks down completely when we move to HDLs.
ASIC CONSTRUCTION
•  The physical design of ASICs is normally divided into system
partitioning, floorplanning, placement, and routing. 
• A microelectronic system is the town and the ASICs are the buildings.
System partitioning corresponds to town planning, ASIC floorplanning
is the architect’s job, placement is done by the builder, and the
routing is done by the electrician.
• We shall design most, but not all, ASICs using these design steps.
Physical Design
CAD Tools
• In order to develop a CAD tool it is necessary to convert each of the physical
design steps to a problem with well-defined goals and objectives.
• The goals for each physical design step are the things we must achieve.
• The objectives for each step are things we would like to meet on the way to
achieving the goals.
• Some examples of goals and objectives for each of the ASIC physical design
steps are as follows:
1. System partitioning:
Goal: Partition a system into a number of ASICs.
Objectives: Minimize the number of external connections between the ASICs. Keep each
ASIC smaller than a maximum size.
2. Floorplanning:
Goal: Calculate the sizes of all the blocks and assign them locations.
Objective: Keep the highly connected blocks physically close to each other.
3. Placement:
Goal: Assign the interconnect areas and the location of all the logic cells within
the flexible blocks.
Objectives: Minimize the ASIC area and the interconnect density.
4. Global routing:
Goal: Determine the location of all the interconnect.
Objective: Minimize the total interconnect area used.
5. Detailed routing:
Goal: Completely route all the interconnect on the chip.
Objective: Minimize the total interconnect length used.