VHDL (First Unit)

VHDL 2
Identifiers, data objects and data types

Chapter2

Data
Identifiers objects Data types

constants Signals Variables

VHDL 2. Identifiers, data objects and data

types ver.9b
 Identifiers
• How to create names?

VHDL 2. Identifiers, data objects and data

types ver.9b
 Identifiers
• Used to represent an
Chapter2
object (constant, signal
or variable ,entity,
architecture)
• Two types Data
Identifiers objects Data types
– Basic identifier
– Extended identifier

constants Signals Variables

VHDL 2. Identifiers, data objects and data

types ver.9b
 Rules for Basic Identifiers
• Names for users to identify data objects:
signals, variables etc.
• First character must be a letter
• last character cannot be an underscore
• Not case sensitive
• Two connected underscores are not allowed
• Examples of identifiers: a, b, c, axy, clk ...

VHDL 2. Identifiers, data objects and data

types ver.9b
 Example:
a,b,equals are Identifiers of signals
• 1 entity eqcomp4 is
• 2 port (a, b: in std_logic_vector(3 downto 0);
• 3 equals: out std_logic);
• 4 end eqcomp4;
• 5
• 6 architecture dataflow1 of eqcomp4 is
• 7 begin
• 8 equals <= '1' when (a = b) else '0’;
• 9-- “comment” equals is active high
• 10 end dataflow1;

VHDL 2. Identifiers, data objects and data

types ver.9b
 Extended Identifier

• They were add in VHDL’93 in order to make

the code more compatible with tools.
Characteristics:
– Contain special characters
– Begin with numbers
– Same name as keywords
– Start with (/),followed by a sequence of
characters ,followed by another backslash(/)
– Case sensitive

VHDL 2. Identifiers, data objects and data

types ver.9b
 Examples
• /a+b/
• /3 state/
• /type/
• Entity example is
port(in_port: in bit;
Bit_port:out bit);
End example

VHDL 2. Identifiers, data objects and data

types ver.9b
Data objects

VHDL 2. Identifiers, data objects and data

types ver.9b
 Data objects
• Constant
Chapter2
• Signals
• variables
Data
Identifiers objects Data types

Constants Signals Variables

(Global) (Global) (Local)

VHDL 2. Identifiers, data objects and data

types ver.9b
 Data objects: 3 different objects
• 1 Constants: hold values that cannot be changed within a
design.
– e.g. constant width: integer 8
• 2 Signals: to represent wire connections
– e.g. signal count: bit_vector (3 downto 0)
– -- count means 4 wires; they are count(3),count(2), count(1),
count(0).
• 3 Variables: internal representation used by programmers;
do not exist physically.

VHDL 2. Identifiers, data objects and data

types ver.9b
 Recall:
if a signal is used as input/output declared in
port
• It has 4 modes e.g.
entity eqcomp4 is
port (a, b: in std_logic_vector(3 downto 0 );
equals: out std_logic);
end eqcomp4;

BUFFER - An output which is also used internally and has a limited fan-out.
We will not use mode BUFFER. This will make it easier to use entities in
hierarchical designs as VHDL is a strongly typed language.
VHDL 2. Identifiers, data objects and data
types ver.9b
Syntax to create data objects
In entity declarations

VHDL 2. Identifiers, data objects and data

types ver.9b
 Constants with initialized values
• constant CONST_NAME: <type_spec> := <value>;
• -- Examples:
• constant CONST_NAME: BOOLEAN := TRUE;
• constant CONST_NAME: INTEGER := 31;
• constant CONST_NAME: BIT_VECTOR (3 downto 0) := "0000";
• constant CONST_NAME: STD_LOGIC := 'Z';
• constant CONST_NAME: STD_LOGIC_VECTOR (3 downto 0) := "0-0-"; --
‘-’ is don’t care

VHDL 2. Identifiers, data objects and data

types ver.9b
 Signals with initialized values
• signal sig_NAME: type_name [: init. Value];
• -- examples
– signal s1_bool : BOOLEAN; -- no initialized value
– signal xsl_int1: INTEGER :=175;
– signal su2_bit: BIT :=‘1’;
– BY DEFAULT value T’LEFT (leftmost value i.e false)

VHDL 2. Identifiers, data objects and data

types ver.9b
 Variables with initialized values
• variable V_NAME: type_name [: init. Value];
• -- examples
– variable v1_bool : BOOLEAN:= TRUE;
– variable val_int1: INTEGER:=135;
– variable vv2_bit: BIT; -- no initialized value

VHDL 2. Identifiers, data objects and data

types ver.9b
 Signal and variable assignments
• SIG_NAME <= <expression>;
• VAR_NAME :=<expression>;

VHDL 2. Identifiers, data objects and data

types ver.9b
Exercise 2.1: Find identifiers, I/O signals, variables, constants,
arrays, and list their data_types.
• 1-- a, b: out bit:
• 2-- CLK, ASYNC ,LOAD, : in STD_LOGIC;
• 3-- DIN: in STD_LOGIC_VECTOR(3 downto 0);
• 4-- DOUT: out STD_LOGIC_VECTOR(3 downto 0);
• 5 process (CLK, ASYNC)
• 6 begin
• 7 if ASYNC='1' then
• 8 DOUT <= "0000";
• 9 elsif CLK='1' and CLK'event then
• 10 if LOAD='1' then
• 11 DOUT <= DIN;
• 12 end if;
• 13 end if;
• 14 end process
VHDL 2. Identifiers, data objects and data
types ver.9b
 Note:
• User can design the type for a data object.
– E.g. a signal can have the type ‘bit’
– E.g. a variable can have the type ‘ std_logic’
• Only same type can interact.

VHDL 2. Identifiers, data objects and data

types ver.9b
 2.2:
Exercise
declare a signal with type bit in line 2
• 1 Architecture test2_arch of test2
• 2 ???????????
• 3 begin
• 4 ...
• 5 …
• 6 end test_arch

VHDL 2. Identifiers, data objects and data

types ver.9b
 Exercise 2.3: Where to specify the types for signals. Draw the
schematic of this circuit.

• 1 entity nandgate is Specify types of signals in either

• 2 port (in1, in2: in STD_LOGIC; (a) port declaration, or
• 3 out1: out STD_LOGIC); (b) before ‘begin’ in architecture
• 4 end nandgate; body
• 5 architecture nandgate_arch of nandgate is
• 6 signal connect1: STD_LOGIC;
• 7 begin
• 8 connect1 <= in1 and in2;
• 9 out1<= not connect1;
• 10 end nandgate_arch;

VHDL 2. Identifiers, data objects and data

types ver.9b
 Types must match
• 1 entity test is port ( Different types :
bit and std_logic
• 2 in1: in bit;
• 3 out1: out std_logic );
• 4 end test;
• 5 architecture test_arch of test is
• 6 begin
• 7 out1<=in1;
• 8 end test_arch;
VHDL 2. Identifiers, data objects and data
types ver.9b
 Revision (so far we learned)
• Data object
– Constants, signal, Variables Chapter2
• Signal in port (external
pins)
– In
– Out Data
– Inout Identifiers objects Data types
– Buffer

Constants Signals Variables

(Global) (Global) (Local)

VHDL 2. Identifiers, data objects and data

types ver.9b
 Exercise 2.4: Revision
What kinds of data objects are in1 and out1?
What is the data type for signal out1?

• 1 entity nandgate is Specify types of signals in either

• 2 port (in1, in2: in STD_LOGIC; (a) port declaration, or
• 3 out1: out STD_LOGIC); (b) before ‘begin’ in architecture
• 4 end nandgate; body
• 5 architecture nandgate_arch of nandgate is
• 6 signal connect1: STD_LOGIC;
• 7 begin
• 8 connect1 <= in1 and in2;
• 9 out1<= not connect1;
• 10 end nandgate_arch;

VHDL 2. Identifiers, data objects and data

types ver.9b
Different data types

VHDL 2. Identifiers, data objects and data

types ver.9b
 Data types
•
Chapter2

Data
Identifiers objects Data types

Constants Signals Variables

(Global) (Global) (Local)

VHDL 2. Identifiers, data objects and data

types ver.9b
 Different data types
Chapter2

Data
Identifiers objects Data types

•
Constants Signals Variables
(Global) (Global) (Local)

VHDL 2. Identifiers, data objects and data

types ver.9b
 Data types

Discrete types

Numeric types

VHDL 2. Identifiers, data objects and data

types ver.9b
 Scalar type
• Is a type whose values have no elements.
• Values cannot contain composite elements.
• All values are in order.Each value of discrete
or numeric have positional number associated
with it.

VHDL 2. Identifiers, data objects and data

types ver.9b
 Enumerated Types
• An enumeration type is defined by listing (enumerating) all possible
values explicitly.
• Declaration Format:
• TYPE type_name IS (enumeration_ident_list);
type std_ulogic is (‘U’,’0’,’1’,’Z’,’W’,’L’,’H’,’-’);
• then we can declare
signal carry : std_ulogic:=‘U’;
• The definition explicitly enumerates all possible values that an
object of this type can assume
• User defined values consisting of identifiers, character literals.
• Every value has position number, starting from 0 and from
leftmost element also next number is one greater than left
number.

VHDL 2. Identifiers, data objects and data

types ver.9b
 Predefined enumeration types

• TYPE bit IS (`0','1');

• TYPE boolean IS (false,true);
• TYPE severity_level IS
(note,warning,error,failure);
Used with assert statements

• TYPE character IS (`a','b','c',...);

VHDL 2. Identifiers, data objects and data
types ver.9b
 More Examples

• TYPE Two_level_logic IS (`0','1');

• TYPE Three_level_logic IS (`0','1','Z');
• TYPE micro_op IS load,add,sub,mul);
• TYPE Opcode IS
(Add,Add_with_carry,Sub,Sub_with_carr
y,Complement);

VHDL 2. Identifiers, data objects and data

types ver.9b
 Difference between “to” and
“downto”
• Given:
• signal a : std_logic_vector( 2 downto 0);
• Create a 3-bit bus c using “to”instead of “downto” in the
declaration.
• Draw the circuit for this statement: c<=a;

VHDL 2. Identifiers, data objects and data

types ver.9b
 Answer
• signal c : std_logic_vector(0 to 2);
• c<=a; means c(0)<=a(2), c(1)<=a(1),
c(2)<=a(0),

VHDL 2. Identifiers, data objects and data

types ver.9b
 Exercises
• Declare an emulation type of the traffic light..
• Declare an emulation type of the 7 notes of
music.
• Answer:type traffic_light is (yellow, green, red, yellow_green);
• signal tr1: traffic_light; -- so tr1 is a signal and can be one of the 5 cases.

VHDL 2. Identifiers, data objects and data

types ver.9b
 Integer type
• Integers are the set of positive and negative whole numbers.
• Upper and lower range constraints must be integer range.
• • Declaration format:
• TYPE type_name IS RANGE int_range_constraint;
• • Predefined integer type:

• TYPE integer IS RANGE –2147483648=[ -2 (31) ] TO 2147483647 = [2 (31) -1];

VHDL 2. Identifiers, data objects and data

types ver.9b
 RANGE
• RANGE
• • Identifies subset of values.
• • May be used with type declarations or object declarations
• Format:
• RANGE begin direction end
• • Direction may be:
• Ascending - TO
• Descending - DOWNTO
• Examples:
• TYPE day IS RANGE 1 TO 31;
• TYPE voltage IS RANGE 12 DOWNTO -12;
• SIGNAL in_volts: voltage RANGE 5 DOWNTO 0; -- object declaration
• with range a subset of the full range of voltage.
• • When the range clause does not appear in an object declaration, the object
assumes the full range of the type which appears in them declaration.

VHDL 2. Identifiers, data objects and data

types ver.9b
Integer type (depends on your tool; it
uses large amount of logic circuits for
the implementation of integer/float
operators) E.g.

• Maximum range from -(2^31-1) to (2^31-1)

e.g.
• variable a: integer range -255 to 255

VHDL 2. Identifiers, data objects and data

types ver.9b
 Floating type
• Floating Points are the set of positive and negative numbers which
contain a decimal point.
• Upper and lower range constraints must contain a decimal point.
• • Declaration format:
• TYPE type_name IS RANGE range_constraint;
• • Predefined floating point type:
• TYPE real IS RANGE -1.79769E308 TO 1.79769E308;

VHDL 2. Identifiers, data objects and data

types ver.9b
 Floating type
• -1.0E38 to 1.0E38
• For encoding floating numbers, but usually
not supported by synthesis tools of
programmable logic because of its huge
demand of resources.

VHDL 2. Identifiers, data objects and data

types ver.9b
 Physical type
• Describes objects in terms of a base unit, multiples of
base unit, and a specified range.
• Declaration format:
• TYPE type_name IS RANGE range_constraints
• UNITS
• base_unit;
• [ -- multiples;]
• END UNITS;
 Examples
• Predefined physical type:
• TYPE time IS RANGE -2**(31-1) TO 2**(31-1)
• UNITS
• fs; --femtosecond =10-15 sec
• ps = 1000 fs; --picosecond =10-12 sec
• ns = 1000 ps; --nanosecond =10-9 sec
• us = 1000 ns; --microsecond =10-6 sec
• ms = 1000 us; --millisecond =10-3 sec
• sec =1000 ms; --second

VHDL 2. Identifiers, data objects and data

types ver.9b
 Example cont…
• min =60 sec; --minute
• hr =60 min; --hour
• END UNITS;

• Example:
• TYPE Resistance IS RANGE 1 TO 10E9
• UNITS
• ohm; --the base unit.
• kohm=1000 ohm; --secondary unit, multiple of base unit.
• END UNITS;

VHDL 2. Identifiers, data objects and data

types ver.9b
 Boolean, Bit Types
• Boolean (true/false), character, integer, real,
string, these types have their usual meanings.
In addition, VHDL has the types: bit,
bit_vector,
• The type “bit” can have a value of '0' or '1'. A
bit_vector is an array of bits.

VHDL 2. Identifiers, data objects and data

types ver.9b
 Examples of some common types
• Type BOOLEAN is (FALSE, TRUE)
• type bit is (‘0’ ,’1’);
• type character is (-- ascii string)
• type INTEGER is range of integer numbers
• type REAL is range of real numbers

VHDL 2. Identifiers, data objects and data

types ver.9b
 Std_ulogic standard
• Type STD_ULOGIC, defined in the package STD_LOGIC_1164,is an
enumeration type as:
• (‘U’--- uninitialized
• ‘x’--- forcing unknown
• ‘0’--- forcing 0
• ‘1’--- forcing 1
• ‘z’--- high impedance
• ‘w’---weak unknown
• ‘L’---Weak 0
• ‘H’--- Weak 1
• ‘-’--- Don’t care);

VHDL 2. Identifiers, data objects and data

types ver.9b
 Define
Array or a bus

VHDL 2. Identifiers, data objects and data

types ver.9b
 Array type

• Multiple values of same type under single identifier.

• • One or more dimensions
• the position of each element in an array is given by a scalar value
called index. referenced by indices.
• Indices type must be integer or enumeration.
• • Declaration format:
• TYPE array_type_name IS ARRAY range_constraints) OF type;
• • Predefined array types:
• TYPE string IS ARRAY (positive RANGE <>) OF character;
• TYPE bit_vector IS ARRAY (natural RANGE <>) OF bit;

VHDL 2. Identifiers, data objects and data

types ver.9b
 Example:
• TYPE Column IS RANGE 1 TO 80;
• TYPE Row IS RANGE 1 TO 24;
• TYPE Matrix IS ARRAY (Row,Column) OF
boolean;

VHDL 2. Identifiers, data objects and data

types ver.9b
Constrained or unconstrained.

• Boundaries of constrained array are stated:

• TYPE array_1 IS ARRAY (integer RANGE -10 TO 25) OF
bit;
• TYPE array_1_too IS ARRAY (-10 TO 25) OF bit;
• (NOTE: integer is optional)
• • Boundaries of unconstrained array are left open:
• TYPE array_2 IS ARRAY (integer RANGE <>) OF bit;
• When we declare object of unconstrained type , we
have to provide a constraint that specifies the index
bounds.

VHDL 2. Identifiers, data objects and data

types ver.9b
 example
• Type sample is array (natural range <>) of
integer;
• Now create an object of this unconstrained
type,
• Variable short_ sample: sample(0 to 63);

• This indicate that index value for the variable

short_ sample are natural numbers in the
ascending range 0 to 63.
VHDL 2. Identifiers, data objects and data
types ver.9b
 Array Subtypes:

• Subsets of specified array types.

• Do not define a new array type.
• TYPE that SUBTYPE is based on must be an unconstrained array.
• Declaration format:
• SUBTYPE name IS (array_name RANGE range_constraint);
• Example:
• TYPE data IS ARRAY (natural RANGE <>) OF bit;
• SUBTYPE low_range IS (data RANGE 0 TO 7);
• SUBTYPE high_range IS (data RANGE 8 TO 15);

VHDL 2. Identifiers, data objects and data

types ver.9b
 Advantage of subtypes
• There are several advantages of subtypes. The primary
advantage is to clarify what is being done in the model. They
make it easier to visualize what is being stored and why by
breaking large groupings of values into smaller groupings.
Each "smaller grouping" can have a name which more
descriptively tells what values it represents.

VHDL 2. Identifiers, data objects and data

types ver.9b
 Array Initialization:
1.Initial values for a one-dimensional array type
signal must be placed in a set of parenthesis
and should follow the := symbol in the signal
declarations. The initial values of individual
array elements should be separated by
commas.
• SIGNAL sq4: bit_nibble :=(`1','0','1','1');

VHDL 2. Identifiers, data objects and data

types ver.9b
 Array Initialization cont..

2. Nested sets of parentheses as should be used for multi-

dimensional arrays. In this case, the top level set of parentheses
corresponds to the left-most range of the array.
• TYPE bit_4by8 IS ARRAY(3 DOWNTO 0, 0 TO 7) OF BIT;
• SIGNAL sq_4_8: bit_4by8 :=
(
(`0','0','0','0','1','1','1','1'),
(`0','0','0','1','1','1','1','1')
(`0','0','1','1','1','1','1','1')
(`0','1','1','1','1','1','1','1')
);
VHDL 2. Identifiers, data objects and data
types ver.9b
 Exercise???
• What are aggregates?
• How an aggregate can be used to provide an
initial value to an array object?
• How aggregate specified in constant
declaration?

VHDL 2. Identifiers, data objects and data

types ver.9b
 Record Type
• A second composite type is the records type. A
record consists of multiple elements that may be
of different types.
• The syntax for a record type is the following:
• type name is
• record
•             identifier :subtype_indication;
•                         :
•             identifier :subtype_indication;
• end record;
VHDL 2. Identifiers, data objects and data
types ver.9b
 As an example
• type MY_MODULE  is
• record
•             RISE_TIME     :time;
•             FALL_TIME   : time; Field elements
•             SIZE                : integer range 0 to 200;
•             DATA              : bit_vector (15 downto 0);
• end record;
•             signal A, B: MY_MODULE;
• To access values or assign values to records, one can use one of the following methods:
•              
•             A.RISE_TIME <= 5ns;
• A.SIZE <= 120;
•             B <= A;

VHDL 2. Identifiers, data objects and data

types ver.9b
 Other Example
• type pin_type  is range 0 to 10;
• Type module is
• record
• SIZE                : integer range 0 to 200;
• Critical delay: Time;
•             No_inputs     : pin_type;
•            No_outputs   : pin_type;
      end record;
•             signal nand_comp: MODULE;
• Nand_comp := (50,20ns,3,2);
• To access values or assign values to records, one can use one of the following
methods:
• Nand_comp . No_inputs := 2;
•              

VHDL 2. Identifiers, data objects and data

types ver.9b
 Entity
• Entity declaration
– describes the input/output ports of a module

entity name port names port mode (direction)

entity reg4 is
port ( d0, d1, d2, d3, en, clk : in bit;
q0, q1, q2, q3 : out bit );
end entity reg4; punctuation

reserved words port type

VHDL 2. Identifiers, data objects and data

types ver.9b
 Conti..
• Omit entity at end of entity declaration

entity reg4 is
port ( d0, d1, d2, d3, en, clk : in bit;
q0, q1, q2, q3 : out bit );
end reg4;

VHDL 2. Identifiers, data objects and data

types ver.9b
 Modes
• The NAME_OF_ENTITY is a user-selected identifier
signal_names consists of a comma separated list of one or more user-
selected identifiers that specify external interface signals.
• mode: is one of the reserved words to indicate the signal direction:
• in – indicates that the signal is an input
• out – indicates that the signal is an output of the entity whose value can
only be read by other entities that use it.
• buffer – indicates that the signal is an output of the entity whose value
can be read inside the entity’s architecture
• inout – the signal can be an input or an output.

VHDL 2. Identifiers, data objects and data

types ver.9b
 Architecture
• Architecture body
– describes an implementation of an entity
– may be several per entity
• Behavioral architecture
– describes the algorithm performed by the module
– contains
• process statements, each containing
• sequential statements, including
• signal assignment statements and
• wait statements

VHDL 2. Identifiers, data objects and data

types ver.9b
 Delays
• Three types
– Inertial delay
– Transport delay
– Delta delay

VHDL 2. Identifiers, data objects and data

types ver.9b
 Delay models
• Inertial delay
– Default delay model
– Suitable for modeling delays through devices such as gates
• Transport Delay
– Model delays through devices with very small inertia, e.g., wires
– All input events are propagated to output signals
• Delta delay
– What about models where no propagation delays are specified?
– Infinitesimally small delay is automatically inserted by the simulator to
preserve correct ordering of events

VHDL 2. Identifiers, data objects and data

types ver.9b
 Transport delay
• architecture transport delay of half_adder is
• signal s1, s2: std_logic:= ‘0’;
• begin
• s1 <= (a xor b) after 2 ns;
• s2 <= (a and b) after 2 ns;
• sum <= transport s1 after 4 ns;
• carry <= transport s2 after 4 ns;
• end architecture transport delay;

a Inertial
b
sum

carry Transport

s1

s2

VHDL 2. Identifiers, data objects and data

types ver.9b
 Delta delay
architecture behavior of combinational
signal s1, s2, s3, s4: std_logic:= ‘0’;
• library IEEE; begin
• use IEEE.std_logic_1164.all; s1 <= not In1;
• entity combinational is s2 <= not In2;
• port (In1, In2: in std_logic; s3 <= not (s1 and In2);
• z : out std_logic); s4 <= not (s2 and In1);
• end entity combinational; z <= not (s3 and s4);
end architecture behavior;
s1 s3
In1

In2 s4
s2

VHDL 2. Identifiers, data objects and data

types ver.9b
 IN1

In2
Delta IN2
time
S2
Z
S3
S1
Z
S2
10 Δ 2Δ 3Δ

S3 Internal ordering established

by the simulator

S4

10 20 30 40 50 60 70
 Models
• Data flow
• Behavioral model
• Structure model
• Mixed model

VHDL 2. Identifiers, data objects and data

types ver.9b
 Data flow model
• View of data as flowing through design, from input to output
• An operation is defined in terms of a collection of data
transformation
• Set of concurrent statements
• It used the logical equations
• Level of abstraction is algorithmic or gate
• Need Boolean equation as design specification

VHDL 2. Identifiers, data objects and data

types ver.9b
 example
architecture dataflow of combinational
signal s1, s2, s3, s4: std_logic:= ‘0’;
• library IEEE; begin
• use IEEE.std_logic_1164.all; s1 <= not In1;
• entity combinational is s2 <= not In2;
• port (In1, In2: in std_logic; s3 <= not (s1 and In2);
• z : out std_logic); s4 <= not (s2 and In1);
• end entity combinational; z <= not (s3 and s4);
end architecture behavior;
s1 s3
In1

In2 s4
s2

VHDL 2. Identifiers, data objects and data

types ver.9b
 Difference:
signal variable
• Are declared via signal declaration
• Is declared within a blocks,
statement or entity port definitions.
process,procedure or function.
• May be any data type
• Any scalar or aggregate data type.
• Similar to hardware and are not updated
• Are immediately updated
until the end of the process.
• • They are utilized in behavioral
Use signals for hardware descriptions
descriptions.
• Signals may be slower
• Variables allow quick simulation
• If u assign several values to a signal in
• When you assign a value to a variable
one process, only the final value is used .
,the assignment takes immediately. A
variable maintains its value until specify
new value.

VHDL 2. Identifiers, data objects and data

types ver.9b
 Variable vs. signal
Example: signal
Example: variable
 ARCHITECTURE test1 OF mux IS • ARCHITECTURE test2 OF mux IS
 SIGNAL x : BIT := '1'; • SIGNAL y : BIT := '0';
 SIGNAL y : BIT := '0'; • BEGIN
 BEGIN • PROCESS (in_sig, y)
 PROCESS (in_sig, x, y) • VARIABLE x : BIT := '1';
 BEGIN • BEGIN
 x <= in_sig XOR y; • x := in_sig XOR y;
 y <= in_sig XOR x; • y <= in_sig XOR x;
 END PROCESS; • END PROCESS;
 END test1; • END test2;

VHDL 2. Identifiers, data objects and data

types ver.9b
 Exercise????

• Differentiate between concurrent and

sequential statements

VHDL 2. Identifiers, data objects and data

types ver.9b
 Concurrent statements
• process statement -- behavior
• concurrent procedure call -- behavior
• concurrent signal assign. -- data flow
• component instantiation -- structure
• generate statement -- structure
• block statement -- nesting
• concurrent assertion stmt -- error check
 Behavioral model
• Architecture body
– describes an implementation of an entity
may be several per entity
• Behavioral architecture
– describes the algorithm performed by the module
– contains
• process statements, each containing
• sequential statements, including
• signal assignment statements and
• wait statements

VHDL 2. Identifiers, data objects and data

types ver.9b
Syntax of process in behavioral model
 PROCESS statements are collections of actions executed in sequence. These actions are called
sequential statements. The types of actions include assigning values to signals, conditional
execution, repeated executions etc.
 [process_label:] process [ (sensitivity_list) ] [is]
 [ process_declarations]
 begin
 list of sequential statements such as:
 signal assignments
 variable assignments
 case statement
 exit statement
 if statement
 loop statement
 next statement
 null statement
 procedure call
 wait statement
 end process [process_label];
 Sensitivity list
• Sensitivity list is a list of signals to which the process is
sensitive to. A process gets active (or executed) only when
there is an event on at least one of the signals in the
sensitivity list.

• All “asynchronous input” signals and “clock” signal gets

included in the sensitivity list.

VHDL 2. Identifiers, data objects and data

types ver.9b
 Example half adder
 library IEEE; use IEEE.STD_LOGIC_1164.all;  
 entity ha_beha_en is
 port( A : in BIT; B : in BIT;
 S : out BIT;  C : out BIT );
 end ha_beha_en;    
 architecture ha_beha_ar of ha_beha_en is
 Begin
 process_beh: process(A,B)
 begin
 S<= A xor B;
 C<=A and B;  
 end process process_beh;
   end ha_beha_ar;

VHDL 2. Identifiers, data objects and data

types ver.9b
 Full adder
•  
In1
A sum
  H
A
H
A In3
B
cout
cin In2

sum
a
out
b carry b

ports

VHDL 2. Identifiers, data objects and data

types ver.9b
 EXAMPLE OF FULL ADDER
 library ieee;
 use ieee.std_logic_1164.all;
 entity FULL_ADDER is
 port (A, B, Cin : in std_logic;
 Sum, Cout : out std_logic);
 end FULL_ADDER;
  
 architecture BEHAV_FA of FULL_ADDER is
 signal int1, int2, int3: std_logic;
 begin
 -- Process P1 that defines the first half adder
 P1: process (A, B)
 begin
 int1<= A xor B;
 int2<= A and B;
 end process;
 -- Process P2 that defines the second half adder and the OR -- gate
 P2: process (int1, int2, Cin)
 begin
 Sum <= int1 xor Cin;
 int3 <= int1 and Cin;
 Cout <= int2 or int3;
 end process;
 end BEHAV_FA
 Structure model
 Define the components used in the design
 Describe the interconnection of these
components
 Structural models can be easily generated
from schematics
 Structural descriptions can be nested

VHDL 2. Identifiers, data objects and data

types ver.9b
 Hierarchy and Abstraction
-- top level

full_adder.vhd
half_adder.vhd

or_2.vhd

-- bottom level

and2.vhd xor2.vhd

o Nested structural descriptions to produce hierarchical models

o Behavioral models of components at the bottom level must exist

VHDL 2. Identifiers, data objects and data

types ver.9b
 Structure model (brief)
• Structural architecture
– implements the module as a composition of subsystems
– contains
• signal declarations, for internal interconnections
– the entity ports are also treated as signals
• component instances
– instances of previously declared entity/architecture pairs
• port maps in component instances
– connect signals to component ports

VHDL 2. Identifiers, data objects and data

types ver.9b
Architecture of structure modelling
• architecture architecture_name of NAME_OF_ENTITY is
• -- Declarations
• component declarations
• signal declarations
• begin
• -- Statements
• component instantiation and connections
• :
• end architecture_name;

VHDL 2. Identifiers, data objects and data

types ver.9b
 Component declaration
• component component_name [is]
• [port (port_signal_names: mode type;
• port_signal_names: mode type;
• :
• port_signal_names: mode type);]
• end component [component_name];
 Component Instantiation and
interconnections
• The syntax for the components instantiation is as follows,

• instance_name : component name

• port map (port1=>signal1, port2=> signal2,… port3=>signaln);
• port map (signal1, signal2,…signaln);

VHDL 2. Identifiers, data objects and data

types ver.9b
 Full adder with structure

In1 s1 sum
H H
In2 A A s2
c_out
c_in s3

VHDL 2. Identifiers, data objects and data

types ver.9b
 Entity declaration of full adder
• Entity full_adder is
– Port(In1,In2,c_in: in std_logic;
– Sum,c_out: out std_logic);
End full_adder;

VHDL 2. Identifiers, data objects and data

types ver.9b
Full adder with structure model
architecture structural of full_adder is
component half_adder is -- the declaration
port (a, b: in std_logic; -- of components you will use
sum, carry: out std_logic);
end component half_adder;
unique name of the components
component or_2 is
component type
port(a, b : in std_logic;
interconnection of the component
c : out std_logic);
ports
end component or_2;
signal s1, s2, s3 : std_logic;
begin
H1: half_adder port map (a => In1, b => In2, sum=>s1, carry=>s3);
H2:half_adder port map (a => s1, b => c_in, sum =>sum,
carry => s2);
O1: or_2 port map (a => s2, b => s3, c => c_out);
end architecture structural; component instantiation statement

VHDL 2. Identifiers, data objects and data

types ver.9b
 Exercise???
• Difference between component declaration
and component instantiation.
• Difference between actual and formals.
• What are different types of associations.

VHDL 2. Identifiers, data objects and data

types ver.9b
Structure Example exercise
bit0
d_latch
d0 q0
d q
clk

bit1
d_latch
d1 q1
d q
clk

bit2
d_latch
d2 q2
d q
clk

bit3
d_latch
d3 q3
d q

gate clk
and2
en int_clk
a y
clk
b
 Concurrent signal assignment
• The syntax is as follows:

• Target_signal <= expression;

• Sum <= (A xor B) xor Cin;

• Carry <= (A and B);
• Z <= (not X) or Y after 2 ns;

VHDL 2. Identifiers, data objects and data

types ver.9b