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8086/8088
Hardware Specifications
Name-Jahangir Alam Chanchal
Subject-Microprocessor &Assembly Language
Semester-Spring 20(6cs)
Id Number -666-49-18
Objectives 2
Describe the functions of the 8086 pin.
Understand the microprocessor’s DC
characteristics.
Use the clock generator chip (8284A) to provide
the clock for the microprocessor.
Connect buffers and latches to the buses.
Interpret the timing diagrams.
Explain the difference between minimum and
maximum mode.
8086/8088 Hardware Activity 3
Interface to 8086/8088 Hardware
The 8086 is a 16-bit microprocessor with a 16-bit data bus. As
the pin- outs show, the 8086 has pin connections AD0–AD15
And the 8088 is a 16-bit microprocessor with an 8-bit data
bus. (As the pin- outs show, the 8088 has pin connections
AD0–AD7.
Understand the pin functions and timing
Pin-outs and the pin functions 4
Functions and in some cases the multiple functions of the
microprocessor’s pins.
DC characteristics: a basis for understanding buffering and
latching.
Power Supply Requirement 5
Require +5.0V with a supply voltage tolerance of ±10
percent.
Draws a maximum supply current of 360 mA.
Operates in ambient temperatures of between 32oF and
about 180oF.
There is a CMOS version which requires a very low supply
current and also has an extended temperature range.
DC characteristics 6
This knowledge allows the hardware designer to select the proper
interface components for use with the microprocessor without the
fear of damaging anything
Input/output characteristics of 7
8086
The input characteristics of the 8086 is compatible with all
the standard logic components available today
The logic 1 voltage level of the 8086 is compatible with that
of most standard logic families, but the logic 0 level is not.
Standard logic circuits have a maximum logic 0 voltage of
0.4V, and the 8086 have a maximum of 0.45V.
Thus there is a difference of 0.05V.
Pin Connections 8
READY & RESET 9
Ifthe READY pin is placed at a logic 0 level, the
microprocessor enters into wait states and remain idle.
If the READY pin is placed at a logic 1 level, it has no
effect on the operation of the microprocessor.
The reset input causes the microprocessor to reset itself
if this pin is held high for a minimum of four clocking
periods.
Whenever the 8086 or 8088 is reset, it begins executing
instructions at memory location FFFF0H and disables
future interrupts by clearing the IF flag bit.
MN/MX & ALE 10
The minimum/maximum mode pin selects
either minimum mode or maximum mode
operation for the microprocessor.
If minimum mode is selected, the MN/MX pin
must be connected directly to +5.0V.
Address latch enable shows that the 8086
address/data bus contains address information.
The address can be a memory address or an I/O
port number.
HOLD 11
The hold input request a direct memory access
(DMA).
If the HOLD signal is a logic 1, the microprocessor
stops executing software and places its address,
data, and control at the high-impedance state.
If the HOLD pin is a logic 0, the microprocessor
executes software normally.
Pin Functions 12
The 8284A is an 18-pin integrated circuit designed
specifically for use with the 8086 microprocessors.
8284A Pin-out
AEN1 and AEN2 (active 13
low)
The bus ready inputs are provided in
conjunction with the AEN1 and AEN2 pins
to cause wait states in an 8086-based system.
RDY1 and RDY2
The address enable pins are provided to
qualify the bus ready signals, RDY1 and
RDY2, respectively.
ASYNC (active low) & 14
READY
The ready synchronization selection input
selects either one or two stages of
synchronization for the RDY1 and RDY2
inputs.
Ready is an output pin that connects to the
8086 READY input.
This input is synchronized with the RDY1
and RDY2 inputs.
X1,X2 & F/C 15
The crystal oscillator pins connect to an
external crystal used as the timing source for
the clock generator and all its functions.
The frequency/crystal select input chooses the
clocking source for the 8284A.
EFI & CLK 16
The external frequency input is used when the
F/C pin is pulled high.
EFI supplies the timing whenever the F/C pin is
high.
The clock output pin provide the CLK input
signal to the 8086 microprocessors and other
components in the system.
PCLK & OSC 17
The peripheral clock signal is one-sixth the
crystal or EFI input frequency and has a 50
percent duty cycle.
It provides a clock signal to the peripheral
equipment in the system.
The oscillator output is a TTL level signal that
is at the same frequency as the crystal or EFI
input
RES (active low) & RESET 18
The reset input is an active-low input to the
8284A.
It is often connected to an RC network that
provides power-on resetting.
The reset output is connected to the 8086
RESET input pin.
CSYNC ,GND & Vcc 19
The clock synchronization pin is used
whenever the EFI input provides
synchronization in systems with multiple
processors.
If the internal crystal oscillator is used, this
pin must be grounded.
The ground pin connects to ground
This power supply pin connects to +5.0V
with a tolerance of ±10 percent.
Internal Block Diagram 20
Clock generator (8284A) 21
The clock generator (8284A) and
the 8086 microprocessor illustrating
the connection for the clock and
reset signals.
A 15 MHz crystal provides the 5
MHz clock for the microprocessor.
Bus Buffering and Latching 22
Before the 8086 microprocessor can be used with memory
or I/O interfaces, their multiplexed buses must be
demultiplexed.
DE multiplexing the Buses 23
The address/data bus on the 8086 is multiplexed to reduce
the number of pins required for the 8086 integrated circuit.
Unfortunately, this burdens the hardware designer with the
task of extracting or demultiplexing information from these
multiplexed pins.
DE multiplexing the 8086 24
The 8086 system requires separate address, data, and
control buses.
The following figure shows 8086 with a DE multiplexed
address bus.
This is the model used to build many 8086-based systems.
Connect buffers and latches
to the buses 25
Basic Bus Operation 26
The 8086/8088 microprocessors use the memory and I/O in
periods of time called bus cycles.
Each bus cycle equals four system-clocking periods (T
states).
Some new microprocessors divide the bus cycle into as few
as two clocking periods.
If the clock is operated at 5 MHz (the basic operation.
Difference between minimum 27
and maximum mode operation
In minimum mode there can be only one processor i.e. 8086. ALE
for the latch is given by 8086 as it is the only processor in the
circuit.
In maximum mode there can be multiple processors with 8086,
like 8087 and 8089.Direct control signals M/¯IO, ¯RD. ALE for the
latch is given by 8288 bus controller as there can be multiple
processors in the circuit.
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Thanks
