FPGA Design for Embedded
[Video Title]
Systems
FPGA Design for Embedded Systems
Hardware Description
[Instructor Name(s)]
Languages for Logic Design
[Department Name]
Copyright © 2019 University of Colorado
Objectives
• Explore the history of VHDL
[Video Title] • Methods for learning VHDL
• Syntax and practice
Copyright © 2019 University of Colorado
What is VHDL?
• VHDL is a programming language
[Video Title] • VHDL is structured to
• Describe
• Model (Simulate)
• Synthesize (Translate) into digital electronics
• VHDL has abstraction levels
• Transistor (AND, Flip-Flop)
• Complete System (Hierarchy Levels)
Copyright © 2019 University of Colorado
What is VHDL?
• VHDL is an IEEE standard
• V = VHSIC
[Video Title] • VHSIC = Very High Speed Integrated Circuit
• HDL = Hardware Description Language
• VHDL was a project sponsored by the US
Government and the Air Force which
began in 1980
References: Dr. Yaser Khalifa, 2003/09/17, Introduction to VHDL.
Available: www.engr.newpaltz.edu/~khalify/VHDL.pdf Copyright © 2019 University of Colorado
Learning to “Speak” VHDL
• Strategies for learning any language
• Reduction (Basic elements)
[Video Title] • Immersion (Simulation, Synthesis)
• Repetition (Practice)
• First phrases
• Start with useful phrases (Skeleton)
• Deconstruct “grammar” (syntax) elements
Copyright © 2019 University of Colorado
VHDL Keywords
• Reserved words (short list)
• Can not be used as identifiers
• Ex. do not use “access” as a bus name
access after alias all attribute block
body buffer bus constant exit file
for function generic group in is
label loop mod new next null
of on open out range rem
return signal shared then to type
until use variable wait while with
Reference : Bryan Mealy, Fabrizio Tappero, 2012/01/13,
FREE RANGE VHDL : freerangefactory.org
Copyright © 2019 University of Colorado
Example: 4-bit Comparator in VHDL
A
B
Result
Copyright © 2019 University of Colorado
VHDL Modeling
• Structural modeling (Gate-level)
• Library defined primitive gates (and2/or2)
• Boolean, bitwise logical (and/or)
• Library user defined functions (and17)
• Dataflow modeling
• Use assignment and select statements
• Behavioral modeling
• Use assignments within a process
• process(A, B) , sensitivity list of A, B signals
Copyright © 2019 University of Colorado
4-bit Comparator – Structural Description
-- Use standard IEEE library
library IEEE;
use IEEE.std_logic_1164.all;
-- Entity
[Video Title]
entity Comparator is port (
A,B : in std_logic_vector(3 downto 0);
Result : out std_logic);
end Comparator;
use work.gatespkg.all;
-- Architecture
-- Structural gate description
architecture struct of Comparator is
signal x : std_logic_vector(3 downto 0);
begin
u3: xnor2 port map (A(3), B(3), X(3));
u2: xnor2 port map (A(2), B(2), X(2));
u1: xnor2 port map (A(1), B(1), X(1));
u0: xnor2 port map (A(0), B(0), X(0));
u4: and4 port map (X(3), X(2), X(1), X(0), Result);
end struct;
Copyright © 2019 University of Colorado
4-bit Comparator – Boolean Description
-- Use standard IEEE library
library IEEE;
use IEEE.std_logic_1164.all;
-- Entity
entity Comparator is port (
A,B : in std_logic_vector(3 downto 0);
Result : out std_logic);
end Comparator;
-- Architecture
-- Boolean logic description
architecture bool of Comparator is
begin
Result <= not(A(3) xor B(3)) and
not(A(2) xor B(2)) and
not(A(1) xor B(1)) and
not(A(0) xor B(0));
end bool;
Copyright © 2019 University of Colorado
4-bit Comparator – Dataflow Description
-- Use standard IEEE library
library IEEE;
use IEEE.std_logic_1164.all;
-- Entity
entity Comparator is port (
A,B : in std_logic_vector(3 downto 0);
Result : out std_logic);
end Comparator;
-- Architecture
-- Dataflow description
architecture dataflow of Comparator is
begin
Result <= '1' when (A=B) else '0';
end dataflow;
Copyright © 2019 University of Colorado
4-bit Comparator – Behavioral Description
-- Use standard IEEE library
library IEEE;
use IEEE.std_logic_1164.all;
-- Entity
entity Comparator is port (
A,B : in std_logic_vector(3 downto 0);
Result : out std_logic);
end Comparator;
-- Architecture
-- Behavioral description
architecture behavioral of Comparator is
begin
CompareProcess : process(A, B)
begin
if (A=B) then
Result <= '1';
else
Result <= '0';
end if;
end process CompareProcess;
end behavioral;
Copyright © 2019 University of Colorado
Summary
• History and definition of VHDL
• An approach to learning VHDL, involving
assimilation of vocabulary, phrases and
syntax
• Initial design examples : 4-bit comparator
• Structural, Boolean, Dataflow, Behavioral
Copyright © 2019 University of Colorado
