INSTRUCTION ADDRESSING

MODES & FORMATS

CHAPTER # 8 Computer Organization & Architecture
 Addressing Modes
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 Immediate
 Direct
 Indirect
 Register
 Register Indirect
 Displacement (Indexed)
 Stack

Chapter # 8 Computer Organization & Architecture 2

 Immediate Addressing
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 Operand is part of instruction

 Operand = address field
 e.g. ADD 5
 Add 5 to contents of accumulator
 5 is operand
 No memory reference to fetch data
 Fast
 Limited range

Chapter # 8 Computer Organization & Architecture 3

 Immediate Addressing Diagram
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Instruction

Opcode Operand

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 Direct Addressing
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 Address field contains address of operand

 Effective address (EA) = address field (A)
 e.g. ADD A
 Add contents of cell A to accumulator
 Look in memory at address A for operand
 Advantages:
 Single memory reference to access data
 No additional calculations to work out effective address
 Disadvantages:
 Limited address space

Chapter # 8 Computer Organization & Architecture 5

 Direct Addressing Diagram
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Instruction
Opcode Address A

Memory

Operand

Chapter # 8 Computer Organization & Architecture 6

 Indirect Addressing
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 Memory cell pointed to by address field contains the

address of (pointer to) the operand
 EA = (A)
 Look in A, find address (A) and look there for operand
 e.g. ADD (A)
 Add contents of cell pointed to by contents of A to

accumulator

Chapter # 8 Computer Organization & Architecture 7

 Indirect Addressing
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 Advantage:
 Large address space available
 2n where n = word length
 Disadvantage:
 Instruction execution requires two memory references to
fetch the operand
 One to get its address and a second to get its value
 Hence slower
 May be nested, multilevel, cascaded
 e.g. EA = (((A)))

Chapter # 8 Computer Organization & Architecture 8

 Indirect Addressing Diagram
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Instruction
Opcode Address A

Memory

Pointer to operand

Operand

Chapter # 8 Computer Organization & Architecture 9

 Register Addressing
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 Operand is held in register named in address filed

 EA = R
 Advantages:
 Very fast execution
 Only a small address field is needed in the instruction
 Shorter instructions
 Faster instruction fetch
 No time-consuming memory references are required
 Disadvantage:
 The address space is very limited
 Limited number of registers
Chapter # 8 Computer Organization & Architecture 10
 Register Addressing
S H E H E R YAR MALI K

 Multiple registers helps performance

 Requires good assembly programming or compiler writing
 C programming
 register int a;
 Also called Register Direct addressing

Chapter # 8 Computer Organization & Architecture 11

 Register Addressing Diagram
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Instruction
Opcode Register Address R

Registers

Operand

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 Register Indirect Addressing
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 EA = (R)
 Operand is in memory cell pointed to by contents of
register R
 Large address space (2n)
 One fewer memory access than indirect addressing

Chapter # 8 Computer Organization & Architecture 13

 Register Indirect Addressing Diagram
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Instruction

Opcode Register Address R

Memory

Registers

Pointer to Operand Operand

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 Displacement Addressing
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 Combines the capabilities of direct addressing and register indirect

addressing
 EA = A + (R)
 Requires that the instruction have two address fields, at least one
of which is explicit
 A = base value
 The value contained in one address field is used directly
 R = register that holds displacement
 The other address field’s contents are added to A to produce the effective address
 or vice versa
 Most common uses:
 Relative addressing
 Base-register addressing
 Indexing

Chapter # 8 Computer Organization & Architecture 15

 Displacement Addressing Diagram
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Instruction
Opcode Register R Address A

Memory

Registers

Pointer to Operand + Operand

Chapter # 8 Computer Organization & Architecture 16

 Relative Addressing
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 A version of displacement addressing

 R = Program counter, PC
 EA = A + (PC)
 i.e. get operand from A cells from current location pointed to by PC
 The implicitly referenced register is the program counter (PC)
 The next instruction address is added to the address field to produce
the EA
 Typically the address field is treated as a twos complement number
for this operation
 Thus the effective address is a displacement relative to the address
of the instruction
 Exploits the concept of locality

Chapter # 8 Computer Organization & Architecture 17

 Base-Register Addressing
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 A holds displacement
 R holds pointer to base address
 R may be explicit or implicit
 e.g. segment registers in 80x86
 Exploits the locality of memory references
 Convenient means of implementing segmentation
 In some implementations a single segment base register is
employed and is used implicitly
 In others the programmer may choose a register to hold
the base address of a segment and the instruction must
reference it explicitly
Chapter # 8 Computer Organization & Architecture 18
 Indexed Addressing
S H E H E R YAR MALI K

 The method of calculating the EA is the same as for base-register

addressing
 An important use is to provide an efficient mechanism for performing
iterative operations
 Good for accessing arrays
 Autoindexing
 Automatically increment or decrement the index register after each reference to it
 EA = A + R
 EA = A + R
 R++
 A = base
 The address field references a main memory address and the
 R = displacement
 referenced register contains a positive displacement from that address

Chapter # 8 Computer Organization & Architecture 19

 Indexed Addressing
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 Postindexing
 Indexing is performed after the indirection
 EA = (A) + (R)
 Preindexing
 Indexing is performed before the indirection
 EA = (A + (R))

Chapter # 8 Computer Organization & Architecture 20

 Stack Addressing
S H E H E R YAR MALI K

 A stack is a linear array of locations

 Sometimes referred to as a pushdown list or last-in-first-out queue
 Items are appended to the top of the stack so that the block is
partially filled
 Associated with the stack is a pointer whose value is the
address of the top of the stack
 The stack pointer is maintained in a register
 Thus references to stack locations in memory are in fact register
indirect addresses
 Operand is (implicitly) on top of stack
 e.g.
 ADD Pop top two items from stack and add

Chapter # 8 Computer Organization & Architecture 21

 Addressing Modes Summary
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Chapter # 8 Computer Organization & Architecture 22

 Addressing Modes Summary
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Chapter # 8 Computer Organization & Architecture 23

 x86 Addressing Modes
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 Virtual or effective address is offset into segment

 Starting address plus offset gives linear address
 This goes through page translation if paging enabled
 12 addressing modes available
 Immediate
 Register operand
 Displacement
 Base
 Base with displacement
 Scaled index with displacement
 Base with index and displacement
 Base scaled index with displacement
 Relative
Chapter # 8 Computer Organization & Architecture 24
 x86 Addressing Mode Calculation
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Chapter # 8 Computer Organization & Architecture 25

 x86 Addressing Mode Calculation
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Chapter # 8 Computer Organization & Architecture 26

 ARM Addressing Modes Load/Store
S H E H E R YAR MALI K

 Data processing instructions

 Use either register addressing or a mixture of register and
immediate addressing
 For register addressing the value in one of the register
operands may be scaled using one of the five shift operators
 Branch instructions
 The only form of addressing for branch instructions is
immediate
 Instruction contains 24 bit value
 Shifted 2 bits left so that the address is on a word boundary
 Effective range +/-32MB from from the program counter
 Indirectly through base register plus offset
 Offset added to or subtracted from base register contents to
form the memory address

Chapter # 8 Computer Organization & Architecture 27

 ARM Addressing Modes Load/Store
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 Preindex
 Memory address is formed as for offset addressing
 Memory address also written back to base register
 So base register value incremented or decremented by offset value
 Postindex
 Memory address is base register value
 Offset added or subtracted
 Result written back to base register
 Base register acts as index register for preindex and postindex
addressing
 Offset either immediate value in instruction or another
register
 If register scaled register addressing available
 Offset register value scaled by shift operator
 Instruction specifies shift size

Chapter # 8 Computer Organization & Architecture 28

 ARM Indexing Methods
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Chapter # 8 Computer Organization & Architecture 29

 Instruction Formats
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 Layout of bits in an instruction

 Includes opcode
 Includes (implicit or explicit) operand(s)
 Usually more than one instruction format in an
instruction set

Chapter # 8 Computer Organization & Architecture 30

 Instruction Length
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 Affected by and affects

 Memory size
 Memory organization
 Bus structure
 CPU complexity
 CPU speed
 Trade off between powerful instruction repertoire
and saving space

Chapter # 8 Computer Organization & Architecture 31

 Address Mapping
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 Address modification
 Base, displacement
 Base, index, displacement

Chapter # 8 Computer Organization & Architecture 32

 Allocation of Bits
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 Number of addressing modes

 Number of operands
 Register versus memory
 Number of register sets
 Address range
 Address granularity

Chapter # 8 Computer Organization & Architecture 33

 Improvements
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 Use hexadecimal rather than binary

 Code as series of lines
 Hex address and memory address
 Need to translate automatically using program
 Add symbolic names or mnemonics for instructions
 Three fields per line
 Location address
 Three letter opcode
 If memory reference: address
 Need more complex translation program

Chapter # 8 Computer Organization & Architecture 34

 PDP-8 Instruction Format
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Chapter # 8 Computer Organization & Architecture 35

 PDP-10 Instruction Format
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Chapter # 8 Computer Organization & Architecture 36

 Variable-Length Instructions
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 Variations can be provided efficiently and compactly

 Increases the complexity of the processor
 Does not remove the desirability of making all of the
instruction lengths integrally related to word length
 Because the processor does not know the length of the
next instruction to be fetched a typical strategy is to fetch a
number of bytes or words equal to at least the longest
possible instruction
 Sometimes multiple instructions are fetched

Chapter # 8 Computer Organization & Architecture 37

 PDP-11 Instruction Format
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Chapter # 8 Computer Organization & Architecture 38

 VAX Instruction Examples
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Chapter # 8 Computer Organization & Architecture 39

 x86 Instruction Format
S H E H E R YAR MALI K

Chapter # 8 Computer Organization & Architecture 40

 x86 Instruction Format
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 Instruction prefixes
 Instruction prefix
 The instruction prefix, if present, consists of the LOCK prefix or one
of the repeat prefixes
 The LOCK prefix is used to ensure exclusive use of shared memory in
multiprocessor environments
 The repeat prefixes specify repeated operation of a string, which
enables the x86 to process strings much faster than with a regular
software loop
 There are five different repeat prefixes: REP, REPE, REPZ, REPNE, and
REPNZ

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 x86 Instruction Format
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 Segment override
 Explicitly specifies which segment register an instruction should use,
overriding the default segment-register selection generated by the
x86 for that instruction
 Operand size
 An instruction has a default operand size of 16 or 32 bits, and the
operand prefix switches between 32-bit and 16-bit operands
 Address size
 The processor can address memory using either 16- or 32-bit
addresses
 The address size determines the displacement size in instructions
and the size of address offsets generated during effective address
calculation

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 x86 Instruction Format
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 Opcode
 The opcode field is 1, 2, or 3 bytes in length
 The opcode may also include bits that specify if data is
byte- or full-size (16 or 32 bits depending on context),
direction of data operation (to or from memory), and
whether an immediate data field must be sign extended
 ModR/M
 This byte provide addressing information
 The ModR/M byte specifies whether an operand is in a
register or in memory
 If it is in memory, then fields within the byte specify the
addressing mode to be used
Chapter # 8 Computer Organization & Architecture 43
 x86 Instruction Format
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 SIB
 Certain encoding of the ModR/M byte specifies the inclusion of
the SIB byte to specify fully the addressing mode
 The SIB byte consists of three fields
 Scale field (2 bits) specifies the scale factor for scaled indexing
 Index field (3 bits) specifies the index register
 Base field (3 bits) specifies the base register
 Displacement
 When the addressing-mode specifier indicates that a
displacement is used, an 8-, 16-, or 32-bit signed integer
displacement field is added
 Immediate
 Provides the value of an 8-, 16-, or 32-bit operand
Chapter # 8 Computer Organization & Architecture 44
 ARM Instruction Formats
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Chapter # 8 Computer Organization & Architecture 45

 Thumb Instruction Set
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Chapter # 8 Computer Organization & Architecture 46