Control Unit Implemntation
A Basic Computer Model
Control Unit: It directs/control the main operations by sending to the data path . It flows
between CPU, I/O, memory submodules etc.
Clocking Other inputs Opcode
T0 Inst1
T1 inst2
Logic T2 Control Signal inst3
T3 inst4 Decoder
Circuit .. Generator ..
Tn inst5
Control Signals
Two types: 1. Microprogrammed Control Unit 2. Hardwired Control Unit
Example Simple Processor & Data Paths
MIPS Data Paths with
Generation of Control Signals
A Simple Computer & its Control Unit
Control Signal Sources
• Clock
— One micro-instruction (or set of parallel micro-instructions)
per clock cycle
• Instruction Register
— Op-code for current instruction
— Determines which micro-instructions are performed
• Flags
— State of CPU
— Results of previous operations
• From Control Bus
— Interrupts / Bus Requests
— Acknowledgements
Control Signals Outputs
• Within CPU
—Cause data movement
—Activate specific functions
• Via Main Bus
—To memory
—To I/O modules
Control Signals
Fetch Cycle
• Address of next instruction is in PC
• Address (MAR) is placed on address bus
t1: MAR (PC)
• Control unit issues READ command
• Result (data from memory) appears on data bus
• Data from data bus copied into MBR
t2: MBR (memory)
• PC incremented by 1 (in parallel with data fetch from memory)
PC (PC) +1
• Data (instruction) moved from MBR to IR
t3: IR (MBR)
• MBR is now free for further data fetches
Fetch Cycle
Fetch Cycle:
t1: MAR (PC)
t2: MBR (memory)
PC (PC) +1
t3: IR (MBR)
Fetch Cycle
• Let Tx be the time unit of the clock. Then:
t1: MAR (PC)
t2: MBR (memory)
PC (PC) +1
t3: IR (MBR)
• Is this equally correct? Why?
t1: MAR (PC)
t2: MBR (memory)
t3: PC (PC) +1
IR (MBR)
Basic Rules for Clock Cycle Grouping
• Proper sequence must be followed
— MAR (PC) must precede MBR (memory)
• Conflicts must be avoided
— Must not read & write same register at same time
— MBR (memory) & IR (MBR) must not be in same cycle
• Also: PC (PC) +1 involves addition
— Use ALU ?
— May need additional micro-operations
Indirect Cycle
Indirect Cycle: • IR is now in same state as if direct
t1: MAR (IRaddress) addressing had been used
t2: MBR (memory)
t3: IRaddress (MBRaddress)
• (What does this say about IR size?)
Interrupt Cycle
Interrupt Cycle: • This is a minimum. May be additional
micro-ops to get addresses
t1: MBR (PC)
t2: MAR save-address
• N.B. saving context is done by
PC routine-address
interrupt handler routine, not micro-
t3: memory (MBR)
ops
Execute Cycle: ADD R1, memory
Execute Cycle: ADD R1, X • Different for each instruction
t1: MAR (IRaddress)
t2: MBR (memory) •Note no overlap of micro-operations
t3: R1 R1 + (MBR)
Execute Cycle: ISZ X
Execute Cycle: ISZ X (inc and skip if zero)
t1: MAR (IRaddress) • Notes:
t2: MBR (memory) • “if” is a single micro-operation
t3: MBR (MBR) + 1 • Micro-operations done
t4: memory (MBR) during t4
if (MBR) == 0 then
PC (PC) + 1
Execute Cycle: BSA X
Execute: BSA X (Branch and Save Address) • BSA X - Branch and save address
Address of instruction following
t1: MAR (IRaddress)
BSA
MBR (PC) is saved in X
t2: PC (IRaddress)
• Execution continues from X+1
memory (MBR)
t3: PC (PC) + 1
Control Signals
Control Unit with Decoded Inputs
Internal Organization
• Usually a single internal bus
• Gates control movement of data onto and
off the bus
• Control signals control data transfer to
and from external systems bus
• Temporary registers needed for proper
operation of ALU
Functions of the Control Unit –
•It coordinates the sequence of data movements into, out of,
and between a processor’s many sub-units.
•It interprets instructions.
•It controls data flow inside the processor.
•It receives external instructions or commands to which it
converts to sequence of control signals.
•It controls many execution units(i.e. ALU, data buffers and
registers) contained within a CPU.
•It also handles multiple tasks, such as fetching, decoding,
execution handling and storing results.
• X,Y, temp are transparent to the
programmer /ALU buffer
• Never referenced by any
instruction
• Never used to store data
generated by instruction which
will be required for the other
instruction later.
There are two types of control units:
•Hardwired control unit and
•Microprogrammed control unit.
Control Unit: It directs/control the main operations by sending to the data path . It flows
between CPU, I/O, memory submodules etc.
Clocking Other inputs Opcode
T0 Inst1
T1 inst2
Logic T2 Control Signal inst3
T3 inst4 Decoder
Circuit .. Generator ..
Tn inst5
Control Signals
Hardwired Control Unit: Here, the control signals that are important for
instruction execution control are generated by specially designed hardware logical
circuits, in which we can not modify the signal generation method without physical
change of the circuit structure
WMFC/
• Both decoder provide separate line each step/instruction
Generation of end signal END signal starts a new instruction cycle by resetting the
control step courting
• If (WMFC=1) the step counter stops
counting.
• MFC signal from memory subsystem
resets the FF
MEMR
MEMW J WMFC
clk
MFC K
Hard Wired Control Unit
• The Cycles (Fetch, Indirect, Execute,
Interrupt) are constructed as a State
Machine
• The Individual instruction executions can
be constructed as State Machines
— Common sections can be shared. There is a
lot of similarity
• One ALU is implemented. All instructions
share it
State Machine
•Combinational logic
—Determine outputs at each state.
—Determine next state.
•Storage elements
—Maintain state representation.
State Machine
Inputs Combinational Outputs
Logic Circuit
Storage
Clock Elements
State Diagram
Shows states and actions that cause transitions between states.
Example State Machine
Inputs
Outputs
Next States
Master-slave
flipflops
Problems With Hard Wired Designs
• Sequencing & micro-operation logic gets
complex
• Difficult to design, prototype, and test
• Resultant design is inflexible, and difficult
to build upon (Pipeline, multiple
computation units, etc.)
• Adding new instructions requires major
design and adds complexity quickly.
State Machine for Example Simple Processor
http://highered.mcgraw-hill.com/sites/dl/premium/0072467509/instructor/104653/figurec9.xls
Micro-Programmed Control
Generation of Microinstruction
Microinstruction for fetching a instruction
Microprogrammed Control
Unit:
Fetch the next instructions
Decode Instruction
Ix Iy Iz
to D, B, E F, H, G E, H
t1 C, A, H G D, A, C
t2 G, C B, C
Generate the AND-OR logic circuit. e.g. A= Ixt1+Izt1 =t1(Ix+Iy)
# Microprogrammed(Wilkes) Control unit
Design:
Decode Line Control Signal Address of Next Micro
Activated Generated Instruction
000 C0, C4, C6, C7 000
001 C1, C3 010
010 C2, C4 011
011 C0, C3, C5, C6 ?
Either
011 C0, C3, C5, C6 If true than address 110
110 C0, C1, C7 111
111 C0, C4, C5, C7 Load next instruction in IR
Or
011 C0, C3, C5, C6 If false than address 100
100 C0, C7 101
101 C3, C5, C6 111
111 C0, C4, C5, C7 Load next instruction in IR
Example Simple Processor Micro-Programed Control
Control Unit Organization
The Control Memory contains
sequences of microinstructions
that provide the control signals
to execute instruction cycles,
e.g. Fetch, Indirect, Execute,
and Interrupt.
Tasks of Control Unit:
• Microinstruction sequencing
• Microinstruction execution
May be expected to complete
instruction execution in “1” clock
cycle. How is this possible?
Recall: Micro-sequencing
Example of Control Memory Organization
Microinstructions:
• Generate Control Signals
• Provide Branching
Horizontal vs Vertical Microprogramming
Horizontal Microprogrammed or
— Unpacked
— Hard
— Direct
Vertical Microprogrammed or
— Packed
— Soft
— Indirect
Typical Microinstruction Formats
Microinstruction Encoding - Direct Encoding
Microinstruction Encoding - Indirect Encoding
Horizontal Micro-programming
• Wide control memory word
• High degree of parallel operations possible
• Little encoding of control information
• Faster
Vertical Micro-programming
• Width can be much narrower
• Control signals encoded into function codes –
need to be decoded
• More complex, more complicated to program,
less flexibility
• More difficult to modify
• Slower
Example Microprogramming Formats
• MicroProgram Counter
• Subroutines
• Stack
• Control Register (MicroProgram Format)
Next Address Decision
• Depending on ALU flags and control buffer register:
— Get next instruction
– Add 1 to control address register
— Jump to new routine based on jump microinstruction
– Load address field of control buffer register into control address
register
— Jump to machine instruction routine
– Load control address register based on opcode in IR
Microprogrammed Control Unit
Design Considerations
• Necessity of speed
• Size of Microinstructions
• Address generation
—Branches
– Both conditional and unconditional
– Based on current microinstruction, condition flags,
contents of IR
– Based on format of address information
+ Two address fields
+ Single address field
+ Variable format
Branch Control: Two Address Fields
Branch based upon:
• Instruction Opcode
• Address 1
• Address 2
Does require a wide
microinstruction, but no
address calculation is needed
Branch Control: Single Address Field
Branch based upon:
• Next instruction
• Address
• Opcode
Does require more
circuitry, e.g. adder
Branch Control: Variable Format
One bit determines
microinstruction
format:
• Control signal format
• Branch format
Does require even
more circuitry, and is
slowest.
Advantages and Disadvantages of
Microprogramming
Advantage:
• Simplifies design of control unit
— Cheaper to design
— Less error-prone
— Much easier to modify
— Supports having multiple versions / models
Disadvantage:
• Slower
• More expensive to produce in quantities
