Fall 2020 ECE 445 - Computer Organization 1

MIPS MACHINE LANGUAGE

AND PROGRAM EXECUTION
ECE 445 – Computer Organization
Dr. Craig Lorie
Electrical and Computer Engineering
Lecture #4
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Topics Covered
• MIPS Machine Language Instructions
• R-type, I-type, and J-type Formats
• Conversion from assembly language to machine language
• Conversion from machine language to assembly language
• Program Execution
• High-level and Low-level languages
• Compiler, Assembler, Linker, and Loader
• Instruction Cycle
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Reading Assignment
• Hennessey/Patterson: A.10
• Hennessey/Patterson: 2.1 – 2.7
• Additional reading posted on Blackboard.
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MIPS MACHINE LANGUAGE

Instruction Formats (R, I, and J)
Examples: Convert AL to ML
Examples: Convert ML to AL
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Machine Language
• Low-level programming language.
• “close to” the hardware.
• Architecture dependent.
• Processor specific.
• Cannot be executed on a different processor.

• Assembler translates assembly language instructions into

machine language instructions.
• Each AL instruction corresponds to one ML instruction.
• Machine-readable form (of the low-level instructions)
• Composed of 0’s and 1’s.
• Bits organized into fields (according to instruction formats).
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MIPS Machine Language

• Use the instruction formats (R, I, and J) to translate assembly
language instructions into machine language instructions.
31 26 25 21 20 16 15 11 10 6 5 0
opcode Rs Rt Rd shamt funct R-type

31 26 25 21 20 16 15 0
opcode Rs Rt immediate I-type

31 26 25 0
opcode address J-type

R-type: Opcode bits [31 – 26] + funct bits [5 – 0] are used to specify the instruction
I-type and J-type: Opcode bits [31 – 26] are used to specify the instruction
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Example: R-type Instruction

• Convert the given MIPS AL instruction to a MIPS ML instruction.

add $s0, $s1, $t1 Instruction type: R

(see MIPS Reference Card)

31 26 25 21 20 16 15 11 10 6 5 0

0 17 9 16 0 32
opcode Rs Rt Rd shamt funct

31 26 25 21 20 16 15 11 10 6 5 0

000000 10001 01001 10000 00000 100000

0000 0010 0010 1001 1000 0000 0010 0000 (binary)

0x02298020 (hexadecimal)
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Example: I-type Instruction

• Convert the given MIPS AL instruction to a MIPS ML instruction.

addi $t2, $s4, 27 Instruction type: I

(see MIPS Reference Card)
31 26 25 21 20 16 15 0

8 20 10 27
opcode Rs Rt immediate

31 26 25 21 20 16 15 0
001000 10100 01010 0000000000011011

0010 0010 1000 1010 0000 0000 0001 1011 (binary)

0x228A001B (hexadecimal)
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MIPS Branch Instructions

Description Assembly Instruction Register Transfer Notation Format
branch on equal beq Rs, Rt, immediate If R[Rs] = R[Rt] PC = PC + 4 + (imm. << 2) I
branch on not equal bne Rs, Rt, immediate If R[Rs] != R[Rt] PC = PC + 4 + (imm. << 2) I

beq $s6, $s7, L1

• Branch condition is evaluated. PC = Program Counter
• If condition is true, PC = address of labeled instruction
• else PC = address of next instruction in sequential order.

• Branch instructions use PC-relative addressing.

• Branch Target Address = PC + 4 + (immediate << 2)

Calculate branch target address using contents of PC

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Example: Branch Instruction

• Convert the MIPS branch instruction to a MIPS ML instruction.
0x10000000 beq $s1, $s2, L1 Instruction type: I
0x10000004 … (see MIPS Reference Card)
0x10000008 … Immediate value = (Branch target address – (Branch address + 4)) / 4
0x1000000C … = (0x10000010 – (0x10000000 + 4)) / 4
0x10000010 L1: add $t0, $t1, $t2
= (0x0000000C) / 4 = (12) / 4 = 3
31 26 25 21 20 16 15 0

4 17 18 3
opcode Rs Rt immediate

31 26 25 21 20 16 15 0

000100 10001 10010 0000 0000 0000 0011

0001 0010 0011 0010 0000 0000 0000 0011 (binary)

0x12320003 (hexadecimal)
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MIPS Jump Instructions

Description Assembly Instruction Register Transfer Notation Format
jump j label PC = address of instruction at label J
jump register jr Rs PC = R[Rs] R
R[31] = PC + 4;
jump and link jal label PC = address if instruction at label J

• Jump instructions use a 26-bit address field.

• Jump target address = (PC + 4)[31:28] : address field : 00

upper 4 bits of PC 26-bit address field multiply by 4

(or left-shift by 2 bits)
Jump to instruction at this address (label).

j L2
mnemonic
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Example: Jump Instruction

• Convert the MIPS jump instruction to a MIPS ML instruction.
0x10000000 j L2 Instruction type: J
0x10000004 … (see MIPS Reference Card)
0x10000008 … Jump target address = 0x10000010
0x1000000C … = 0b 0001 0000 0000 0000 0000 0000 0001 0000
0x10000010 L2: add $t0, $t1, $t2
31 26 25 0

2 00 0000 0000 0000 0000 0000 0100

opcode address

31 26 25 0

000010 00 0000 0000 0000 0000 0000 0100

0000 1000 0000 0000 0000 0000 0000 0100 (binary)

0x08000004 (hexadecimal)
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MIPS Machine Language Instructions

• MIPS branch and jump instructions.

Loop: sll $t1, $s3, 2 80000 0 0 19 9 4 0

add $t1, $t1, $s6 80004 0 9 22 9 0 32

lw $t0, 0($t1) 80008 35 9 8 0

bne $t0, $s5, Exit 80012 5 8 21 2

addi $s3, $s3, 1 80016 8 19 19 1

j Loop 80020 2 20000

Exit: … 80024
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PROGRAM EXECUTION
Programming languages (high-level, assembly, machine)
Compiler, assembler, linker, and loader
Instruction cycle
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High-Level, Assembly, and Machine

High-level Language
• Portable
• Can be executed on any processor
for which there is a compiler.

Assembly Language (Low-level)

• Processor-specific
• Cannot be executed on a different
processor.
• Human-readable form.

Machine Language (Low-level)

• Processor-specific
• One-to-one correlation with
assembly language instructions.
• Machine-readable form.
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Creating an Executable Program

Compiler
• Translates HLL program
into assembly language.
• Processor-specific.
Assembler
• Translates assembly
language into machine
language.
• Creates an object file.
Linker
• Combines multiple object
files, including library files,
into a single executable
program.
Loader
• Loads the executable
program into memory.
• Prepares it for execution.
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Program Execution
• The processor executes machine language (ML) instructions.
• Stored program computer
• ML instructions are stored in program memory, each at a specific address.
• Each instruction must be fetched from memory before it can be executed
by the processor (CPU).
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Program Execution
• The processor executes machine language (ML) instructions.
• Special purpose registers
• Program Counter (PC): stores the address of the instruction to be fetched.
• Instruction Register (IR): stores the instruction to be executed by the CPU.

Program Counter

Instruction Register
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Program Execution
• Each machine language instruction is processed according to
the steps in the instruction cycle.
• Aka. the fetch-execute cycle and the CPU cycle.

Instruction
Fetch

Instruction
Decode

Execute

Instruction Cycle
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Instruction Cycle
• Each machine language instruction is processed according to
the steps in the instruction cycle.

IF
Instruction Fetch
• PC contains address of ML instruction.
• Read (fetch) instruction from program
memory at address pointed to by PC.
ID
• Adjust PC to point to next instruction.
• Increment PC (by 4 for MIPS)
• Use Branch target address

EX • Use Jump target address

Instruction Cycle
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Instruction Cycle
• Each machine language instruction is processed according to
the steps in the instruction cycle.

IF
Instruction Decode
• Instruction is identified by the opcode
(and the funct bits for MIPS R-type
instructions).
ID • Control unit decodes instruction.
• Appropriate control signals are generated.
• Control the functional units in the datapath

EX needed to execute the instruction.

• Control unit generates a different set of control
Instruction Cycle signals for different instructions.
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Instruction Cycle
• Each machine language instruction is processed according to
the steps in the instruction cycle.

IF
Execute
• Functional units in the datapath
implement the required actions for the
executed instruction.
ID • Functional units controlled by the control
signals.
• Different instructions require a different set
of actions and, thus, a different set of
EX functional units.

Instruction Cycle
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Questions?