Designing Combinational Lo
gic Gates in CMOS
Prepared By: Engr. MM
Outline
Introduction
Static CMOS Design
Complementary CMOS
Ratioed Logic
Pass-Transistor Logic
Dynamic CMOS Design
Dynamic Logic: Basic Principles
Speed and Power Dissipation of
Dynamic Logic
Issues in Dynamic Design
Cascading Dynamic Gates
Perspectives
How to Choose a Logic Style?
Designing Logic for Reduced Supply
Voltages
Summary
Introduction
Combinational VS Sequential
Non-regenerative circuits—circuits that have the Regenerative circuits—circuits for which the output is
property that at any point in time, the output of the not only a function of the current input data, but also of
previous values of the input signals. This is
circuit is related to its current input signals by some
accomplished by connecting one or more outputs
Boolean expression (assuming that the transients intentionally back to some inputs. Consequently, the
through the logic gates have settled). No intentional circuit “remembers” past events and has a sense of
connection between outputs and inputs is present. history.
Introduction
The primary advantage of the CMOS structure:
robustness (i.e, low sensitivity to noise)
good performance, and
low power consumption with no static power dissipation.
• The complementary CMOS circuit style falls under a broad class of logic circuits called static circuits in
which at every point in time (except during the switching transients), each gate output is connected to
either VDD or Vss via a low-resistance path.
• Also, the outputs of the gates assume at all times the value of the Boolean function implemented by the
circuit (ignoring, once again, the transient effects during switching periods).
• This is in contrast to the dynamic circuit class, which relies on temporary storage of signal values on the
capacitance of high-impedance circuit nodes. The latter approach has the advantage that the resulting
gate is simpler and faster. Its design and operation are however more involved and prone to failure due to
an increased sensitivity to noise.
Static CMOS Design
Complementary CMOS
Ratioed logic (pseudo-NMOS and DCVSL),
Pass-transistor logic
Static CMOS Design
Complementary CMOS
Ratioed logic (pseudo-NMOS and DCVSL),
Pass-transistor logic
Static CMOS Design
Complementary CMOS
A static CMOS gate is a combination of two networks, called the pull-up network (PUN) and
the pull-down network (PDN)
Complementary logic gate as a combination of a PUN
(pull-up network) and a PDN (pull-down network).
Static CMOS Design
Complementary CMOS
In constructing the PDN and PUN networks, the following observations should be kept in mind:
• A transistor can be thought of as a switch controlled by its gate signal. An NMOS switch is on
when the controlling signal is high and is off when the controlling signal is low. A PMOS
transistor acts as an inverse switch that is on when the controlling signal is low and off when
the controlling signal is high.
• The PDN is constructed using NMOS devices, while PMOS transistors are used in the PUN.
The primary reason for this choice is that NMOS transistors produce “strong zeros,” and PMOS
devices generate “strong ones”.
Static CMOS Design
Complementary CMOS
Simple examples
illustrate why an
NMOS should be
used as a pull-
down, and a
PMOS should be
used as a pull-up
device.
Static CMOS Design
Complementary CMOS
• A set of construction rules can be derived to construct logic functions. NMOS devices
connected in series corresponds to an AND function. With all the inputs high, the series
combination conducts and the value at one end of the chain is transferred to the other end.
• Similarly, NMOS transistors connected in parallel represent an OR function.
Static CMOS Design
Complementary CMOS
• Using De Morgan’s theorems ((A + B) = A·B and A·B = A + B), it can be shown that the pull-
up and pull-down networks of a complementary CMOS structure are dual networks. This
means that a parallel connection of transistors in the pull-up network corresponds to a series
connection of the corresponding devices in the pull-down network, and vice versa.
Therefore, to construct a CMOS gate, one of the networks (e.g., PDN) is implemented using
combinations of series and parallel devices.
• The complementary gate is naturally inverting, implementing only functions such as NAND,
NOR, and XNOR. The realization of a non-inverting Boolean function (such as AND OR, or
XOR) in a single stage is not possible, and requires the addition of an extra inverter stage.
• The number of transistors required to implement an N-input logic gate is 2N.
Static CMOS Design
Complementary CMOS
P-type
A B Q1 Q2 Q3 Q4 Z
L L ON ON OFF OFF H
L H ON OFF OFF ON H
N-type H L OFF ON ON OFF H
H H OFF OFF ON ON L
This is a two-input NAND
_____ Gate.
Static CMOS Design
Complementary CMOS
Example: Synthesis of complex CMOS Gate
Using complementary CMOS logic, consider the synthesis of a complex CMOS
gate whose function is F = D + A· (B +C).
Static CMOS Design
Complementary CMOS
Ratioed logic (pseudo-NMOS and DCVSL),
Pass-transistor logic
Static CMOS Design
Complementary CMOS
Ratioed logic (pseudo-NMOS and DCVSL),
• Ratioed logic is an attempt to reduce the number of transistors required to implement a
given logic function, at the cost of reduced robustness and extra power dissipation.
• The purpose of the PUN in complementary CMOS is to provide a conditional path
between VDD and the output when the PDN is turned off.
• In ratioed logic, the entire PUN is replaced with a single unconditional load device that
pulls up the output for a high output. Instead of a combination of active pull-down and
pull-up networks, such a gate consists of an NMOS pull-down network that realizes the
logic function, and a simple load device.
Static CMOS Design
Complementary CMOS
Ratioed logic (pseudo-NMOS and DCVSL),
Static CMOS Design
Complementary CMOS
Ratioed logic (pseudo-NMOS and DCVSL),
Pass-transistor logic
A popular and widely-used alternative to
complementary CMOS is pass-transistor logic,
which attempts to reduce the number of
transistors required to implement logic by
allowing the primary inputs to drive gate
terminals as well as source/drain terminals.
This is in contrast to other previous logic
families, which only allow primary inputs to Pass-transistor implementation of an AND gate.
drive the gate terminals of MOSFETS.
Dynamic CMOS Design Dynamic Logic: Basic Principles
The basic construction of an (n-type) dynamic logic gate is shown below. The PDN (pull-down network) is
constructed exactly as in complementary CMOS. The operation of this circuit is divided into two major phases:
precharge and evaluation, with the mode of operation determined by the clock signal CLK.
Dynamic CMOS Design Dynamic Logic: Basic Principles
Precharge
When CLK = 0, the output node Out is precharged to VDD by the PMOS transistor Mp. During that time,
the evaluate NMOS transistor Me is off, so that the pull-down path is disabled. The evaluation FET
eliminates any static power that would be consumed during the precharge period (this is, static current
would flow between the supplies if both the pulldown and the precharge device were turned on
simultaneously).
Evaluation
For CLK = 1, the precharge transistor Mp is off, and the evaluation transistor Me is turned on. The output
is conditionally discharged based on the input values and the pull-down topology. If the inputs are such
that the PDN conducts, then a low resistance path exists between Out and GND and the output is
discharged to GND. If the PDN is turned off, the precharged value remains stored on the output
capacitance CL, which is a combination of junction capacitances, the wiring capacitance, and the input
capacitance of the fan-out gates. During the evaluation phase, the only possible path between the output
node and a supply rail is to GND. Consequently, once Out is discharged, it cannot be charged again till
then next precharge operation. The inputs to the gate can therefore make at most one transition during
evaluation. Notice that the output can be in the high-impedance state during the evaluation period if the
pull-down network is turned off. This behavior is fundamentally different from the static counterpart that
always has a low resistance path between the output and one of the power rails.
Dynamic CMOS Design Dynamic Logic: Basic Principles
A number of important properties can be derived for the dynamic logic gate:
• The logic function is implemented by the NMOS pull-down network. The
construction of the PDN proceeds just as it does for static CMOS.
• The number of transistors (for complex gates) is substantially lower than in
the static case: N + 2 versus 2N.
• It is non-ratioed. The sizing of the PMOS precharge device is not important
for realizing proper functionality of the gate. The size of the precharge device
can be made large to improve the low-to-high transition time (of course, at a
cost to the high-to low transition time). There is however, a trade-off with power
dissipation since a
larger precharge device directly increases clock-power dissipation.
Dynamic CMOS Design Dynamic Logic: Basic Principles
• It only consumes dynamic power. Ideally, no static current path ever exists
between VDD and GND. The overall power dissipation, however, can be
significantly higher compared to a static logic gate.
• The logic gates have faster switching speeds. There are two main reasons for
this. The first (obvious) reason is due to the reduced load capacitance
attributed to the lower number of transistors per gate and the single-transistor
load per fan-in. Second, the dynamic gate does not have short circuit current,
and all the current provided by the pull-down devices goes towards discharging
the load capacitance.
