Pipeline II

Hazards
 Real World Analogy:: Resources Hazard
• There are three different types of hazard relate to pipelining one of these hazards is explained using Car
Manufacture pipeline example.
• Assume that we one have one employee that assembles and paints the car as well.
• LHS table shows the ideal case, but there is a conflict of resource here, P and A cannot be done at same time.
• This is called resource hazard with one object cannot proceed in pipeline because the resource need by it is
busy with other object.
• RHS table show that one solution can be that car 2 waits for A until P of car1 is complete (Car 3 waits for A till
P of Car 2 is complete)
• Another solution can be to add more resources, in this case hire another employee for paint job

Time 1st 2nd 3rd 4th 5th Time 1st 2nd 3rd 4th 5th 6th 7th
line hour hour hour hour hour line hour hour hour hour hour hour hour
Car 1 A P T Car 1 A P T
Car 2 A P T Car 2 idle A P T
Car 3 A P T Car 3 idle A P T
Pipeline Hazard in Computer
• A pipeline hazard occurs when the pipeline, or some portion of the
pipeline, must stall because conditions do not permit continued execution.
• Such a pipeline stall is also referred to as a pipeline bubble.
• Three Hazard types:
• Structural/Resource
• same resource is needed multiple times in the same cycle
• Data
• Instruction depends on result of prior instruction still in the pipeline data dependencies limit
pipelining
• Control
• Next executed instruction may not be the next specified instruction
Pipeline Hazard in Computer

Can always resolve hazards by stalling

More stall cycles = more CPU time = less performance

Increase performance = decrease stall cycles

• The result is that the instructions must be executed in serial rather than parallel for a portion of
the pipeline.
• Examples:
• Two accesses to a single ported memory
• Two operations need the same function unit
at the same time
• Two operations need the same function unit
in successive cycles, but the unit is not pipelined
• Solutions:
• stalling
• add more hardware
Structural/Resource Hazard:: Example
• Assume the there is only
single port to memory
• FO of I1 and FI of I3, both
require reading from
memory at cycle 3
• Assume that for operand for
rest of the Instructions are
registers.
• There resource conflict
between I1 and I3
• I3 must wait
Data Hazards
• Data hazards occur when the pipeline changes the order of read/write
accesses to operands so that the order differs from the order seen by
sequentially executing instructions on an unpipelined processor.
• Three types of data dependencies defined in terms of how succeeding
instruction depends on preceding instruction
• RAW: Read after Write or Flow dependency
• WAR: Write after Read or anti-dependency
• WAW: Write after Write
RAW
• Read After Write (RAW)
InstrJ tries to read operand before InstrI writes it
• I: ADD AX, BX
• J: SUB CX, AX
Write after read (WAR) or antidependency
• An instruction reads a register or memory location and a succeeding
instruction writes to the location.
• A hazard occurs if the write operation completes before the read
operation takes place.
• I: read from location X
• J: write to location X
• Incorrect answer if J finishes before I
Write after write (WAW), or output
dependency
• Two instructions both write to the same location.
• A hazard occurs if the write operations take place in the reverse order
of the intended sequence.
• I: write to location X
• J: write to location X
• Incorrect answer if J finishes before I
Data Hazard
• Solution
• Stalling
• Logic Detection
• Data Forwarding
• Used in RAW dependency, data is forwarded to next instruction as soon as its available
so that next instruction doesn’t have to wait for write operand
• Needs changes in hardware
Control Hazard
• A control hazard, also known as a branch hazard
• Occurs when the pipeline makes the wrong decision on a branch
prediction and therefore brings instructions into the pipeline that
must subsequently be discarded
• If instruction 3 was conditional branching
• Until the instruction is actually executed, it is impossible to determine whether the branch will be taken or not.
• If I3 takes jump to I15, all the work done for i4-i7 is wasted
Dealing with Branches
• A variety of approaches have been taken for dealing with conditional
branches
• Multiple streams
• Pre-fetch branch target
• Loop buffer
• Branch prediction
• Delayed branch
Branch Prediction
■ Predict never taken
■ Predict always taken
■ Predict by opcode
■ Taken/not taken switch
■ Branch history table
Reference
• Section 14.4 (Pipeline Hazards) from Computer Organization and
Architecture Designing for Performance Tenth Edition, by William
Stalling
• http://www.cs.uni.edu/~
fienup/cs240s05/lectures/lec5_1-25-05_web.htm
• http://faculty.cse.tamu.edu/djimenez/614-spring14/bpred.html