Islamic University of Technology

EEE 4483
Digital Electronics & Pulse Techniques

Lecture- 9
Digital Counters

• In electronics, counters can be implemented quite easily using register-

type circuits such as the flip-flop, and a wide variety of designs exist,
e.g.:
• Asynchronous (ripple) counters
• Synchronous counters
• Johnson counters
• Decade counters
• Up-Down counters
• Ring counters
• There are several ways to create counter circuits, such as using T flip-
flop, D flip-flop, JK flip-flop. In this class, we will introduce a simply
way to write code in VHDL for the counter.
VHDL Example: Gated D Latch

The code in Figure 7.36 defines an

entity named latch, which has the
inputs D and Clk and the output
Q. The process uses an if-then-
else statement to define the value
of the Q output. When Clk=1, Q
takes the value of D. When Clk =
0, Q will retain its current value in
this case, and the code describes a
gated D latch.
The process sensitivity list includes
both Clk and D because these
signals can cause a change in the
values of the Q output.
VHDL Example: D Flip-Flop
This is a example for a positive-
edge-triggered D flip-flop.

1. The process sensitivity list

contains only the clock
signal because it is the only
signal that cause a change
in the Q output.
2. The syntax Clock’EVENT
uses a VHDL construct
called an attribute. With
condition Clock = 1, here it
means that ”the value of the
Clock signal has just
changed, and the value is
now equal to 1”, which
refers to a positive clock
edge.
VHDL Example: A Four-bit Up-Counter
Resetn: Reset input
E: enable input
In the architecture body the flip-
flops in the counter are
represented by the signal
named Count
If E=1, the count is incremented
If E=0, the code explicitly
assigns Count<=Count
The O outputs are assigned the
values of Count at the
end fo the code.
Introduction to Clock
In electronics and especially
synchronous digital circuits, a clock
signal is a signal used to coordinate
the actions of two or more circuits. A
clock signal oscillates between a
high and a low state and is usually in
the form of a square wave.
Slow down the Clock

• The Altera DE2 board includes two oscillators that produce 27 MHz and
50 MHz clock signals.

• However, the high frequency will make the seven segment display
looks like on all the time, and the eyes of human can not distinguish
the change.

One way to slow down the clock frequency is to write a DivClk.vhd

file, with the help of IF-ELSE statement and a variable to count the
high frequency signal to generate a low frequency signal.
Structure Descriptions in VHDL
• Once we have defined the basic building blocks of our design using entities and their associated
architectures, we can combine them together to form other designs.
VHDL Testbench

• Testing a design by simulation

• Use a test bench model
• an architecture body that includes an instance of the design under test
• applies sequences of test values to inputs
• monitors values on output signals
• either using simulator
• or with a process that verifies correct operation
VHDL Testbench : continued ..

¨ VHDL test bench is VHDL code that produces

stimuli to test your design correctness
¨ It can automatically verify accuracy of the
VHDL code
¨ Given a known input, does the system
generate the expected output
¨ Verifies that the VHDL code meets the
circuits specifications
¨ Test benches should be easily modified,
allowing for future use with other code
¨ Should be Easy to understand the behavior
of the test bench

10
VHDL Testbench : continued ..
What Is The VHDL Test Bench (TB)?
VHDL test bench (TB) is a piece of VHDL code, which purpose is to verify
the functional correctness of HDL model.

The main objectives of TB is to:

– Instantiate the design under test (DUT)
– Generate stimulus waveforms for DUT
– Generate reference outputs and compare them with the outputs of
DUT
– Automatically provide a pass or fail indication

Test bench is a part of the circuits specification.

Its a good idea to design the test bench before the DUT, why?
Stimulus and Response

Three ways how TB can generate the stimulus:

– Generate them “on-the-fly”
– Read vectors stored as constants in an array
– Read vectors stored in a separate system file

Response is produced in the test bench.

Response can be stored into file for further processing.

Example:
– Stimulus can be generated with Matlab and TB feeds it into DUT.
– DUT generates the response and TB stores it into file.
– Result can be compared to Matlab simulations.
Testbench Structures

• TB should be reusable without difficult modifications.

• The structure of the TB should be simple enough so that other
people understand its behavior.
• Good test bench propagates all the generics and constants into
DUT.
• Question: How to verify that the function of the test bench is
correct?
Testbench Example
LIBRARY ieee; BEGIN
USE ieee.std_logic_1164.ALL;
-- Instantiate the Unit Under Test (UUT)
ENTITY tb_mux IS uut: mux_4to1 PORT MAP (
END tb_mux; A => A, B => B, C => C, D => D, S0 =>
S0, S1 => S1, Z => Z
ARCHITECTURE behavioral OF tb_mux IS );
-- Component Declaration for the Unit -- Stimulus process
Under Test (UUT) stim_proc: process
begin
COMPONENT mux_4to1 -- hold reset state for 100 ns.
PORT( wait for 100 ns;
A, B, C, D : IN std_logic;
S0 : IN std_logic; A <= '1'; B <= '0'; C <= '1'; D <= '0';
S1 : IN std_logic;
Z : OUT std_logic S0 <= '0'; S1 <= '0'; wait for 100 ns;
); S0 <= '1'; S1 <= '0'; wait for 100 ns;
END COMPONENT; S0 <= '0'; S1 <= '1'; wait for 100 ns;
S0 <= '0'; S1 <= '1'; wait for 100 ns;
--Inputs end process;
signal A : std_logic := '0';
signal B : std_logic := '0'; END ARCHITECTURE behavioral;
signal C : std_logic := '0';
signal D : std_logic := '0';
signal S0 : std_logic := '0';
signal S1 : std_logic := '0';

--Outputs
signal Z : std_logic;