COUNTERS

Introduction
A Counter is a device which stores the number of times a particular event or
process has occurred, often in relationship to a clock signal. 

Counters are used in digital electronics for counting purpose, they can count specific
event happening in the circuit.

For example, in UP counter a counter increases count for every rising/falling edge of
clock.

Not only counting, a counter can follow the certain sequence based on our design
like any random sequence 0,1,3,2… .
Introduction
 Counter Classification
Counters are broadly divided into two categories
• Asynchronous counter
• Synchronous counter
  Asynchronous Counter
• In asynchronous counter we don’t use universal clock, only first flip flop
is driven by main clock and the clock input of rest of the following flip
flop is driven by output of previous flip flops. 
  Asynchronous Counter
• It is evident from timing diagram that Q0 is changing as soon as the falling edge of
clock pulse is encountered, Q1 is changing when falling edge of Q0 is
encountered(because Q0 is like clock pulse for second flip flop) and so on. In this
way ripples are generated through Q0,Q1,Q2,Q3 hence it is also
called RIPPLE counter.
  Synchronous Counter
• Unlike the asynchronous counter, synchronous counter has one global
clock which drives each flip flop so output changes in parallel.
• The one advantage of synchronous counter over asynchronous counter
is, it can operate on higher frequency than asynchronous counter as it
does not have cumulative delay because of same clock is given to each
flip flop.
 Synchronous Counter
 Synchronous Counter Timing diagram
Synchronous Counter Vs Asynchronous Counter
3 Bit Asynchronous Counter
3 Bit Asynchronous Counter
3 Bit Asynchronous Counter with T flip flop
3 Bit Asynchronous Counter with T flip flop
No of negative edge of Q2 MSB Q1 Q0 LSB
Clock
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1
State diagram for 3-Bit Asynchronous Counter
4 Bit Asynchronous Counter
4 Bit Asynchronous Counter waveforms
3 bit asynchronous down counter
 3 bit asynchronous down counter
Q

Q1

Q2
 3 bit asynchronous down counter
No of negative edge of Q2 (MSB) Q1 Q0 (LSB)
Clock
1 1 1 1
2 1 1 0
3 1 0 1
4 1 0 0
5 0 1 1
6 0 1 0
7 0 0 1
8 0 0 0
3 bit asynchronous Up/Down counter
3 bit asynchronous Up/Down counter
M Q Q' Y
Q Q'
0 0 0 0
M
0 0 1 0 1 1
0 1 0 1
0 1 1 1 1 1
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1
Y = M'Q + MQ'
3 bit asynchronous Up/Down counter
 Modulus of the Counter & Counting up to a
particular value
• Modulus Counters, or simply MOD counters, are defined based on the number
of states that the counter will sequence through before returning back to its
original value. For example, a 2-bit counter that counts from 002 to 112 in
binary, that is 0 to 3 in decimal, has a modulus value of 4 ( 00 → 1 → 10 → 11,
and return back to 00 ) so would therefore be called a modulo-4, or mod-4,
counter. Note also that it has taken four clock pulses to get from 00 to 11.
• Therefore, a “Mod-N” counter will require “N” number of flip-flops connected
together to count a single data bit while providing 2n different output states, (n
is the number of bits). Note that N is always a whole integer value.
 Modulus of the Counter & Counting up to a
particular value
• 2-Bit ripple counter called as MOD-4 counter Modulus 4 counter.
• 3-Bit ripple counter called as MOD-8 counter 
• 4-Bit ripple counter called as MOD-16 counter 
 MOD-6 Ripple Counter
• Suppose we want to design a MOD-6 counter, how could we do that. First
we know that “m = 6”, so 2n must be greater than 6. As 21 = 2, 22 = 4,
23 = 8, and 8 is greater than 6, then we need a counter with three flip-flops
(N = 3) giving us a natural count of 000 to 111 in binary (0 to 7 decimal).
• Take the MOD-8 counter above, the truth table for the natural count
• As we are constructing a MOD-6 counter, we want the counter to reset
back to zero after a count of 6. However, we can see from the attached
truth table that the count of six gives us the output condition of: QA = 0,
QB = 1, and QC = 1.
 MOD-6 Ripple Counter
• We can decode this output state of 110 (6) to give us a signal to clear
(Clr) the counter back to zero with the help of a 3-input AND gate (TTL
74LS11) and an inverter or NOT gate, (TTL 74LS04).
• The inputs of the combinational logic circuit of the inverter and AND
gate are connected to QA, QB, and QC respectively with the output of
the AND gate at logic level “0” (LOW) for any combinations of the input
other than the one we want.
• In binary code, the output sequence count will look like this: 000, 001,
010, 011, 100, 101. But when it reaches the state of 110 (6), the
combinational logic circuit will detect this 110 state and produce an
output at logic level “1” (HIGH).
MOD-6 Ripple Counter
MOD-6 Ripple Counter
 Decade or BCD Ripple Counter
• A binary coded decimal (BCD) is a
serial digital counter that counts ten
digits .And it resets for every new
clock input. As it can go through 10
unique combinations of output, it is
also called as “Decade counter”. A
BCD counter can count 0000, 0001,
0010, 1000, 1001, 1010, 1011, 1110,
1111, 0000, and 0001 and so on.
Decade or BCD Ripple Counter
 Decade or BCD Ripple Counter
• When the Decade counter is at REST, the count is
equal to 0000. This is first stage of the counter cycle.
When we connect a clock signal input to the counter
circuit, then the circuit will count the binary
sequence. The first clock pulse can make the circuit
to count up to 9 (1001). The next clock pulse
advances to count 10 (1010).
• Then the ports X1 and X3 will be high. As we know
that for high inputs, the NAND gate output will be
low. The NAND gate output is connected to clear
input, so it resets all the flip flop stages in decade
counter. This means the pulse after count 9 will again
start the count from count 0.