Computer Architecture

Lecture 03
 Operational concepts of a Computer
Topics in this chapter:

•Registers
•CPU Registers
•Word
•Memory Organization
•Memory Addresses
•Word Alignment
•Memory Operations
•Primitive Operations
•Register Transfer Language and Assembly Language
•Using CPU Registers
•Branching
•Status Register
•Addressing Modes
•Simple Addressing Modes
•CISC vs RISC
•CISC and RISC Examples
 Registers
In computer architecture, a Processor Register is a quickly accessible location
available to a computer's central processing unit (CPU).

Registers usually consist of a small amount of fast storage, although some registers

have specific hardware functions, and may be read-only or write-only. 

EXAMPLE: An interrupt control register, or ICR, is a hardware register in a

computer chip used to generate interrupts—in response to some event occurring
within the chip or a circuit connected to the chip.

Almost all computers, load data from a larger memory into registers where it is
used for arithmetic operations and is manipulated. Manipulated data is then often
stored back to main memory.
 CPU Registers
• Instruction register (IR): In computing, an instruction register (IR) is the part of a CPU's
control unit that holds the instruction currently being executed or decoded.

• Program counter (PC): A program counter is a register in a computer processor that contains
the address (location) of the instruction being executed at the current time. As each
instruction gets fetched, the program counter increases its stored value by 1.

• Memory address register (MAR): In a computer, the Memory Address Register (MAR) is the

CPU register that either stores the memory address from which data will be fetched from the
CPU, or the address to which data will be sent and stored. In other words, MAR holds
the memory location of data that needs to be accessed.

• Memory data register (MDR): A memory buffer register (MBR) or memory data

register(MDR) is the register in a computer's processor that stores the data being transferred
to and from the immediate access storage.

• General-purpose register: General purpose registers are used to store temporary data and
addresses within the microprocessor.
 Execution

• Word with an example

• Memory Organization
• Instruction Fetch
• Instruction is decoded
– Register Transfer
• Instruction thus is executed
• Results are stored
 Word

• Data is usually accessed in n-bit groups. n is called word length.

• In the example on this slide, the word size is 32 bits.
 Memory Organization
n bits
• Memory consists of huge first word
number of storage cells, each second word
stores 1 bit.

• Data is usually accessed in n-bit

•
groups. n is called word length. •
•
• In the example on this slide, i th word
the word size is 32 bits.

•
•
•
last word

Figure 2.5. Memory words.

 Memory Addresses
• Memory can either be retrieved as one Word or one Byte (8-bit),
addresses. However, for each location are needed.

• A k-bit address memory has 2k memory locations.

• 24-bit memory: 224 = 16,777,216 = 16MB
• 32-bit memory: 232 = 4294967296 = 4GB

• In the examples on previous slides, we saw 32-bit memory address.

 Word Alignment
• Word alignment is how the instructions should be broken into blocks.
• Word-aligned means the instruction is stored at a memory location that's
divisible by 4.
• The instructions that are stored as multiples of the bytes are said to be
aligned in memory, e.g., is given below:

– 32-bit word: word addresses: 0, 4, 8,…. (32 Bit CPU)

4 8 12 16 20 24 28 32

– 64-bit 8word: 16
word addresses:
24 32 0, 8,16,….
40 (6448Bit CPU)
56 64
 Memory Operations

• Load (or Read or Fetch)

– Copy the content. The memory content remains unchanged.
– Registers can be used
• Store (or Write)
– Content of the memory is overwritten
– Registers can be used
 Primitive Operations

• A computer must have instructions capable of performing

four types of operations:
– Data transfers between the memory and the processor registers
– Arithmetic and logic operations on data
– Program control
– I/O transfers
 Register Transfer Language and Assembly Language

• In computer science, Register Transfer Language (RTL) is a kind

of intermediate representation (IR) that is very close to assembly
language. It is used to describe data flow at the register-transfer level of
an architecture.
• Contents of a Memory Location are denoted by placing square brackets
around the name of the location (R1←[LOC], R3 ←[R1]+[R2])
• In above example, the names with square brackets are Memory Locations
and the names without square brackets are Registers as shown in diagram
below.

• While in Assembly language

– Move LOC, R1 = R1←[LOC]
– Add R1, R2, R3 = R3 ←[R1]+[R2]
 Using CPU Registers
• Registers are faster
• Registers hold small sized instructions that are used frequently
• Shorter instructions
• Potential speedup
• Minimize the frequency of memory access as Registers hold data and
instructions that are used frequently so memory does not have to be
accessed every time a frequently used data or instruction is required
which results in a potential speedup of a computer system.
 Branching
• A branch is an instruction in a computer program that can cause a
computer to begin executing a different instruction sequence and thus
deviate from its default behavior of executing instructions in order. 

• Branch (or branching, branched) may also refer to the act of switching

execution to a different instruction sequence as a result of executing a
branch instruction.

• Branch instructions are used to implement control flow in program loops

and conditionals (i.e., executing a particular sequence of instructions only
if certain conditions are satisfied).
 Branching
• The power of computers is their ability to repeat actions and their ability to alter their
operation depending on data. Modern programming languages express these abilities
using control structures. Repeated action (iteration) is done with a while structure.
Alternative control paths (alternation) is done with an if-then-else structure.

• The machine instructions of the processor do not have these structures, nor does
assembly language. When you program in assembly language you must build these
structures out of basic assembly instructions. These basic instructions are
the jump instructions and the conditional branch instructions.

• Jump Instruction:
– j instruction (jump)
• Conditional Branch Instructions:
– beq instruction (branch equal)
– bne instruction (branch not equal)
 Status Register
• A status register, flag register, or condition code register (CCR) is a collection of status flag bits for
a processor. An example of Status Register is the FLAGS register of the x86 architecture.

• The status register is a hardware register that contains information about the state of the processor.
The status register lets an instruction take action based on the outcome of a previous instruction.

• Condition code register / status register

– N (negative)
– Z (zero)
– V (overflow)
– C (carry)
• Different flags are affected by different instructions

• Flags in the status register are modified as effects of arithmetic and bit manipulation operations. For
example, a Z bit may be set if the result of the operation is zero and cleared if it is nonzero.

• Q. What is a Flag?
• A. In programming, a flag is a predefined bit or bit sequence that holds a binary value. Typically, a
program uses a flag to remember something or to leave a sign for another program.
 Addressing Modes
• Q. What is an Instruction Set Architecture (ISA)?
• A. An instruction set architecture (ISA) is an abstract model of a computer. It is also referred
to as architecture or computer architecture. A realization of an ISA is called
an implementation. An ISA permits multiple implementations that may vary in performance.

• Addressing modes are an aspect of the instruction set architecture (ISA) in most central

processing unit (CPU) designs.
• The various addressing modes that are defined in a given ISA define how machine
language instructions in that architecture identify the operand(s) of each instruction.
• In computer programming, Addressing modes are primarily of interest to compiler writers.
 Simple Addressing Modes

• Absolute or direct

• PC-relative

• This is particularly useful in connection with jumps, because typical jumps are to nearby instructions (in a high-level
language most if or while statements)
 Simple Addressing Modes

• Register indirect

CPUs that do not use sequential execution with a program counter are extremely rare. In some CPUs, each
instruction always specifies the address of next instruction. Such CPUs have an instruction pointer that
holds that specified address; it is not a program counter because there is no provision for incrementing it.
Such CPUs include some drum memory computers such as the IBM 650, the SECD machine, and the RTX
32P.
 Simple Addressing Modes

• Skip

• Skip addressing may be considered a special kind of PC-relative addressing mode with a fixed "+1" offset.
 Addressing Modes
• Following are the most commonly used addressing modes:

• Indirect
• Data referred to through a pointer or address.
• Immediate
• Data embedded directly in an instruction or command list.
• Index
• A dynamic offset, typically held in an index register.
• Offset
• An immediate value added to an address.
• Relative
• An address formed relative to another address.
• Post increment
• The stepping up of an address past data used.
• Pre decrement
• The decrementing of an address prior to use.
 Addressing Modes
• Different computer architectures vary greatly as to the number of addressing modes they
provide in hardware. There are some benefits to eliminating complex addressing modes and
using only one or a few simpler addressing modes. 
• It has proven much easier to design CPUs if the only addressing modes available are simple
ones.

• Most RISC architectures have only about five simple addressing modes while CISC architectures
have over a dozen addressing modes.

• A complex instruction set computer (CISC) is a computer in which a single instruction can
execute several low-level operations (such as a load from memory, an arithmetic operation, and
a memory store).

• A reduced instruction set computer (RISC) is one whose instruction set architecture (ISA) allows
it to have fewer cycles per instruction (CPI) than a complex instruction set computer (CISC).

• RISC processors are also used in supercomputers such as the Sunway TaihuLight, which, as of

November 2017, is the world's fastest supercomputer as ranked by the TOP500 project.
 CISC vs RISC
CISC ARCHITECTURE CHARACTERISTICS
• Single instruction can execute multiple low level operations (such as a load from
memory, an arithmetic operation, and a memory store).
• Instruction-decoding logic will be Complex.
• One instruction is required to support multiple addressing modes.
RISC ARCHITECTURE CHARACTERISTICS
• Usually support single operation per instruction.
• Simple Instructions are used in RISC architecture.
• RISC helps and supports few simple data types.
• RISC utilizes simple addressing modes and fixed length instructions.
• RISC permits any register to use in any context.
• One Cycle Execution Time.
• The amount of work that a computer can perform is reduced by separating “LOAD”
and “STORE” instructions.

Most modern computer systems use RISC CPUs today.

 CISC and RISC Examples

• Examples of CISC PROCESSORS

• IBM 370/168 – It was introduced in the year 1970. CISC design is a 32 bit processor and four 64-bit floating point registers.
VAX 11/780 – CISC design is a 32-bit processor and it supports many numbers of addressing modes and machine instructions
which is from Digital Equipment Corporation.
Intel 80486 – It was launched in the year 1989 and it is a CISC processor, which has instructions varying lengths from 1 to 11
and it will have 235 instructions.

• Examples of RISC PROCESSORS

• IBM PowerPC – Primarily used on Apple PCs until 2006 before Apple switched to Intel CPUs.
• Intel Pentium, Pentium II, Pentium III, Pentium IV, Core 2 Duo, Core i3, Core i5, Core i7
• Qualcomm Snapdragon – Developed by Qualcomm technologies for use in powerful new smart phones such as Samsung S
series, Samsung Note series etc.

• In the 21st century, the smart phones and tablet computers such as the iPad and Android devices provided a wide user base for
RISC-based systems. RISC processors are also used in supercomputers such as Summit, which, as of November 2018, is the
world's fastest supercomputer as ranked by the TOP500 project.