Scribd
Upload
33 views

Basics and Hazards of Pipeline Controller

The document discusses a 4-stage pipelined controller. It describes the concept of pipelining where multiple tasks are performed in an overlapped manner to improve parallelism. A 4-stage pipeline includes fetch, decode, execute, and store stages. Hazards like resource hazards, data hazards, and control hazards can occur in a pipeline and cause stalls. Performance is improved through higher throughput and reduced latency via pipelining, though hazards can limit performance gains.

Uploaded by

Mayank Raj
Copyright
© © All Rights Reserved
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
33 views

Basics and Hazards of Pipeline Controller

The document discusses a 4-stage pipelined controller. It describes the concept of pipelining where multiple tasks are performed in an overlapped manner to improve parallelism. A 4-stage pipeline includes fetch, decode, execute, and store stages. Hazards like resource hazards, data hazards, and control hazards can occur in a pipeline and cause stalls. Performance is improved through higher throughput and reduced latency via pipelining, though hazards can limit performance gains.

Uploaded by

Mayank Raj
Copyright
© © All Rights Reserved
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
You are on page 1/ 23

Four-Stage Pipelined

Controller
LITERATURE SURVEY
Presented by
Mayank Raj
2016BEC098

Guided by
Mr. Vaibbhav Taraate
Dr. S. S. Gajre
 Objective
 Concept Of Pipeline
 Multistage Pipeline
 4-stage Pipeline
 Hazards
 Resource
 Data

CONTENT
 Control
 Performance Parameters
 Speed
 Latency
 Throughput
 Opcode, Operand, Addressing Mode
 Instruction
 Timing Sequence
 Reference Architecture
OBJECTIVE
To understand basics of pipeline controller
CONCEPT OF PIPELINE
 It is an implementation technique where multiple tasks are performed in overlapped manner.
(i.e. In the same phase multiple instructions are executed)

 A task is divided into sub tasks and performed independently

 Implementation technique done on hardware.


clock_cycle 1 2 3 4 5 6 7

 Parallelism can be achieved inst_1 fetch_1 decode_1 execute_1 store_1      


inst_2   fetch_2 decode_2 execute_2 store_2    
inst_3     fetch_3 decode_3 execute_3 store_3  
inst_4       fetch_4 decode_4 execute_4 store_4

Clk->
MULTISTAGE PIPELINE
 An operation is divided into multiple stages which are
then executed in pipeline

 More the stages, more the speed up i.e. faster the


operation/instruction is executed

 2-stage : fetch and execute

 3-stage : fetch, decode and execute etc.


4-STAGE
PIPELINE
Includes fetch, decode, execute and store
clock_cycle 1 2 3 4 5 6 7
inst_1 fetch_1 decode_1 execute_1 store_1      
inst_2   fetch_2 decode_2 execute_2 store_2    
inst_3     fetch_3 decode_3 execute_3 store_3  
inst_4       fetch_4 decode_4 execute_4 store_4

Clk->

 Stage 1: Fetch 
Fetch an instruction from
instruction cache every cycle

 Stage 2: Decode
Decodes opcode bits
 Stage 3: Execute   Stage 4: Store  
Perform ALU operation Perform data cache access
HAZARDS
Ø A pipeline hazard occurs when the pipeline, or some
portion of the pipeline, must stall because conditions
do not permit continued execution.

Ø Such a pipeline stall is also referred to as a pipeline


bubble.

Ø A pipeline stall is a delay in execution of an instruction


in order to resolve a hazard.
RESOURCE HAZARDS /
STRUCTURAL HAZARDS
 A resource hazard occurs when two (or more) instructions that are already in the
pipeline need the same resource.

 The result is that the instructions must be executed in serial rather than parallel for
a portion of the pipeline.

 e.g.
1. A single data and/or address bus can not read/write the same memory
location.
2. While mobile data sharing via USB cable, its inaccessible to read mobile files.
DATA HAZARDS
 A data hazard occurs when there is a conflict in the access of an operand location.

 The program produces an incorrect result because of the use of pipelining.

 A data hazard can lead to a pipeline stall when the current operation has to wait for
the results of an earlier operation which has not yet finished.
Example
The basic five units involved are for instruction fetching, operand address generation,
operand fetching, execution and storing results.

Consider two assembly pseudo code,


ADD A B C #A=B+C
SUB D C A #D=C-A
Without operand forwarding
Clock_Cycle 1 2 3 4 5 6 7 8

ADD Fetch_ADD Decode_ADD Read_operand_ADD Execute_ADD  Write_Result    

SUB   Fetch_SUB Decode_SUB Stall Stall Read_operand_SUB  Execute_SUB Write_result

Clk->
With operand forwarding
Clock_Cycle 1 2 3 4 5 6 7

ADD Fetch_ADD Decode_ADD Read_operand_ADD Execute_ADD  Write_Result  

Read Operands
SUB: use result
SUB   Fetch_SUB Decode_SUB Stall  Execute_SUB Write_result
from previous
operation

Clk->
 Operand forwarding (or data forwarding) is an optimization in pipelined CPUs to limit
performance deficits which occur due to pipeline stalls.

 Forwarding is a method of exploiting instruction-level parallelism


i.e. to minimize stall, forwarding is used
 Read After Write (RAW), or true dependency: An instruction modifies a register or
memory location and a succeeding instruction reads the data in that memory or
register location.
• A hazard occurs if the read takes place before the write operation is
complete.
• e.g.
ADD A B C #A=B+C
SUB D C A #D=C-A

 Write After Read (WAR), or antidependency: An instruction reads a register or


memory location and a succeeding instruction writes to the location.
• A hazard occurs if the write operation completes before the read operation
takes place.
• e.g.
SUB D C A #D=C-A
ADD A B C #A=B+C
 Write After Write (WAW), or output dependency: Two instructions both write to
the same location.

• e.g.
ADD A B C #A=B+C
SUB A B C #A=B-C

• A hazard occurs if the write operations take place in the reverse order of the
intended sequence.

• WAR and WAW hazards occur due to concurrency of instructions


CONTROL HAZARDS
 A control hazard, also known as a branch hazard, occurs when the
pipeline makes the wrong decision on a branch prediction and
therefore brings instructions into the pipeline that must subsequently
be discarded.

 Related with conditional branches.

 e.g. dilemma to board the train with same number.


PERFORMANCE
PARAMETERS
• Latency:
 Number of processor clocks it takes for an instruction to have its data available
for used by another instruction
o e.g. Manufacturing of a scissor
 Tells about how well an instruction is performed in relation to another
instruction on the same processor

• Speed up = time taken by non-pipelied implementation


time taken by pipelined implementation

• Throughput: Number of processor clocks it takes for an instruction to execute or


perform its calculation i.e. Number of actions executed or results per unit of time
Latency x Throughput = QueueSize (Number of stages)
OPCODE,OPERAND,
ADDERESSING MODE
 Opcode: It is an instruction that tells processor what to do with the variable or data
written besides it.

 Operand: It is the variable on which the operation is performed.

 Addressing mode: The way in which the operand of an opcode is specified.


INSTRUCTIONS
1. IDLE/NOP/DO NOTHING 1. NOR
2. MOVE 2. XOR
3. ADD 3. XNOR
4. SUB 4. SET
5. MUL 5. SWAP
6. DIV 6. JUMP
7. COMPARE 7. INC
8. REMOVE (CLEAR) 8. DEC
9. READ 9. ROTATE
10.WRITE 10.REVERSE
11.AND 11.BREAK
12.OR 12.PUSH/ POP
13.NOT 13.LEFT SHIFT, RIGHT SHIFT
TIMING SEQUENCE
Ø It’s a diagramatical representation of how set of
instructions interact with each other during a
particular clock cycle

Ø It consists of many rows of different data sequence,


one of them being a clock
REFERENCE ARCHITECTURE
Harvard architecture
• ALU
• Control unit
• Physical separate storage
• Single pathway for instruction and data
• Data memory
• Instruction memory
• I/P & O/P mechanism
REFERENCES
 Wikipedia
 NPTEL
 YouTube
 IEEE
 GOOGLE
 Computer Organization and Architecture, William Stallins
Thank you

You might also like