Lecture-11

POWER ANALYSIS AT CIRCUIT-LEVEL

Dr. Arti Noor

M. Tech (VLSI) Division, CDAC Noida UP.

29-3-2011 LPVD Lecture-11

 Topics

• Network Restructuring and Reorganization.

– Transistor network restructuring.
– Transistor network partitioning and
reorganization.
• Special Latches and FFs.
• Low Power Digital Cell Library.

LPVD Lecture-11
 Network restructuring and Reorganization
• If signal probabilities are known, then restructuring of transistors may
result in low power.

Various transistor reordering techniques :

Transistor Network Restructuring:
• Boolean functions are composed of AND and OR gates. To realize any
Boolean function, one can map it on complex logic gates directly.
• The mapping steps are :
-- Each variable corresponds to N and P transistor pair,
-- For N-Network : serial connection corresponds to AND while
parallel
OR operator.
-- P-network is just reverse of N-network.
-- Inverter optionally can be added.
Example : Y= AB+C
LPVD Lecture-11
LPVD Lecture-11
LPVD Lecture-11
 Network restructuring summary
• Same function can be implemented in different
ways. This results in different timing and power
consumption.
• To do the analysis of timing and power.
• As a general rule : put transition involving
transistors near to output node because often
these have less delay and consume less power.
• Therefore, one has to calculate transition
probability at each input node to evaluate the
circuit.
• A switching level simulation is used to select best
implementation.
LPVD Lecture-11
Transistor Network Partitioning and Reorganization

• Restructuring operation is applied on single complex

logic gate.
• In place of CMOS gate now consider transistor network.
• Partitioning and reorganization concept can be applied to
trade-off between power and delay.
• Network reorganization is composing different transistors
network that can implement same functionality.
• Large Boolean function can not be implemented in single
complex gate because of series and parallel connection
limit of transistors.
• The exact limit of transistors depends upon technology,
system speed, supply voltage.

LPVD Lecture-11
 Network Reorganization
• With a given technology and serial connection
constrains, the aim is to partition and reorganize
circuit for better performance.
• Example:

LPVD Lecture-11
 Network Reorganization
• The choice of network structure increases
exponentially with circuit size for best result.
• For large network hand calculation is not
possible.
• CMOS complex gate generated by reorganization
can not be predesigned.
• Sizing each transistor of gate needs a tool for
automatic layout simulation.
• Power and timing analysis to be performed at
transistor level which is computation intensive.
• Sophisticated CAD tools are required at physical
level. LPVD Lecture-11
 Special Latches and FFs
• Latches and FFs are basic elements used in synchronous
circuits and decide the maximum speed of the system.
• FFs are clocked at the system and thus consumes large
amount of power.
• FFs energy dissipation has two parts :
• Clock energy : dissipated when FF is clocked and data is
unchanged.
• Data Energy : addition to clock energy due to different
data writing in FF.
• Normally Data rate is much lower than clock rate and thus
power saving techniques concentrate on clock energy
reduction. In addition to voltage reduction, capacitance
reduction and change in transistor count to minimize
switching techniques are used to reduce the power.
LPVD Lecture-11
 Flip-Flop and Latch Circuits
• Flip-flop and latch can be implemented in different ways
and each design varies in terms of area, delay and power
consumption.
• The NMOS transistor in place of TG eliminates two phase
non overlapping clock, reduces load capacitance at the
cost of speed and threshold voltage loss.
• Similarly single phase FF is suitable for low power
implementation as compared to two phase clock.
• One has to do SPICE level simulation after including
transistor sizing techniques to select the best
implementation of Latches and FFs.

LPVD Lecture-11
 Flip-Flop and Latch Circuits
• FF contains differential feedback
circuit to drive RS latch.
Four transistors form cross-coupled
feedback inverters.
• RS inputs are precharged and
selectively discharged at
rising edge of clock.
• The RS latch retains data
when clock is low during precharge.
• T provides a path to GND and
prevents latch to have intermediate
values. Only three transistors are
connected to clock and no static
Current when clk stopped. LPVD Lecture-11
 Flip-Flop and Latch Circuits
• Self Gating FF

• Some part of clock energy is consumed by internal clock buffer to

control TGs.

• If there is no change in data then power can be saved by

suppressing the clock switching.
• Power is saved by holding the internal clock signal while external
clock of FF switches. LPVD Lecture-11
 Flip-Flop and Latch Circuits
• Self Gating FF
The below figure shows this idea.
• TG at Clk is used to gate the external clock so that internal clock 
and bar do not switch if not required.
• When D and Q are different
XOR output is one to pass clk.
When  is high TG is off to stop
unnecessary switching
unless D and Q are different.

LPVD Lecture-11
 Flip-Flop and Latch Circuits
• Self Gating FF

• This circuit uses more area and delay, but if input

switching probability is very low as compared to clock
rate then probability of clock disabling is very high.

• The power dissipation depends on transition frequency of

Td and Tclk. When it is less than one, power saving is
more. when it is zero, no dynamic power consumption by
this circuit.

LPVD Lecture-11
 Flip-Flop and Latch Circuits
• Double edge triggered FF
• Data can be latched on both rising and falling edge of clock. Clock
frequency can be halved to achieved same throughput compared to
single edge triggered FF.
• More area is required but FF retains data when clock is not toggling.
• Comparison of both FFs
• SETFF

Ps  Esc f c  Esd f d
• Esc: energy consumed due to clock
• Esd: energy consumed due to data.
• fc: clock frequency and fd is FF
output frequency.
LPVD Lecture-11
 Flip-Flop and Latch Circuits
• DETFF

Pd  0.5 Edc f c  Edd f d

• Normally fd is very small as compared to fc. DETFF area is more as
SETFF, so energies are also larger in this case.
• If Esc=Esd; Edc = 1.3Esc, Edd=1.3Esd, fd=0.4fc then

Ps  1.4 Esc f c
Pd  1.17 Esc f c  0.84 Ps
• DETFF is working at half frequency, so over all 2X time power saving
in clock distribution network.
• Esc/Edc ratio is important at the time of circuit design.

LPVD Lecture-11
 Low Power Digital Cell Library

• Most circuits are synthesized at gate level to meet the

various specifications.

• At gate–level the basic building blocks are gates or cells.

• Quality of gate level synthesis depends upon quality of

cell library.

• Therefore, low power cells are added in library to meet

the power specification.

LPVD Lecture-11
 Low Power Digital Cell Library
Cell Sizes and Spacing
• In top-down cell based design, one has to do trade-off among area,
delay and power by selecting the appropriate sizes of cells.
• Therefore for good low power cell library, one should have cells of
wide range sizes.
• The number of gates of different sizes is approximately four times of
traditional cell library for low power.
• Spacing of cell sizes should be chosen carefully.
• Capacitance distribution profile is considered for spacing.
• Example : normally net capacitance is within 0.1-0.5pF, thus more cell
sizes should be available to drive this range.
• Because of low range of capacitance, lower drive cells should be
spaced closer than higher drive cells like :1X,2X, 3X,5X, 8X, 12X.

LPVD Lecture-11
 Low Power Digital Cell Library
Varieties of Boolean Functions

• After size and spacing the next consideration is on how many

Boolean functions of given inputs (n-inputs) exist.
• For n-input, one has 2n entries at output side with different 0 and 1
combinations.
• Each combination is unique Boolean function thus one can write

2n
M 2
• M is very large for small values of n. For n=3, M=28, thus for n>3 small
number of M Boolean functions are available in cell library. Typically
OR, AND, XOR, AOI, and OAI are available.

LPVD Lecture-11
 Low Power Digital Cell Library
Varieties of Boolean Functions
• Lack of variety of functions
results in inferior circuits. Y  AB
• Implement Y without having inverted input cells and with inverted
input cells. Compare which cell will take less area and power.

• M functions can not be implemented but how many function should

be sufficient for a rich library?
• Among M some are degenerated : output dose not depend on all input
variables. Among non-degenerated some are identical like

Y  AB Y  A B
LPVD Lecture-11
 Low Power Digital Cell Library
Varieties of Boolean Functions
Equivalence of Functions :

• Permutation of input variables.

• Negation of input variables.
• Negation of output

LPVD Lecture-11
 Low Power Digital Cell Library
Varieties of Boolean Functions
P-Equivalence
• Some Boolean function are P equivalent (one
function can be obtained from other by permuting
the inputs)

 Let f (X) and g (X) be two functions and X = { x1 , x2 ,

…, xn}
• Then
 g (X) = f ( (X) )

 where  is a permutation of X
LPVD Lecture-11
 Low Power Digital Cell Library
Varieties of Boolean Functions
P-Equivalence (Permutation of input variables)
• Example

f  x1 x3  x2 x4 ; g  x2 x4  x1 x3
 maps x1  x2 ; x2  x1 ; x3  x4 ; x4  x3
 g ( x)  f ( x)

• This can be used to reduce the number of function by having P

equivalence classes.

Y  AB  C ; Y  AC  B
LPVD Lecture-11
 Low Power Digital Cell Library
Varieties of Boolean Functions
N-Equivalence (Negation of input variables)
 Let f (X) and g (X) be two functions and X = { x1 , x2 ,…, xn}
• Then
 g (X) = f ( (X) )

 where  maps each xi to itself or its complement

• Example :

f  x1  x2  x3 ; g  x1  x2  x3
 maps x1  x1 ; x2  x2 ; x3  x3 ;
 g ( x)  f (x)
LPVD Lecture-11
 Low Power Digital Cell Library
Varieties of Boolean Functions
N-Equivalence (Negation of output)

g ( X )  f ( X ) or g(X)  f ( X )
f  x1  x2 and g  x1.x2
 g( X )  f ( X )
Y  AB  Y  A B and Y  A B
Y  AB  Y  AB LPVD Lecture-11
 Low Power Digital Cell Library
Varieties of Boolean Functions

 NPN-equivalent :
– equivalent under input Negation, input Permutation,
output Negation
 NP-equivalent :
– equivalent under input Negation, input Permutation
 P- equivalent :
– equivalent under input Permutation

• The cell library which covers the more classes , produces

circuits with better quality.
LPVD Lecture-11
 Low Power Digital Cell Library
Varieties of Boolean Functions
Input (n) Fn. No. n variables P-equipv. NP equipv NPN equipv

2n
2
1 4 2 2 1 1

2 16 10 8 3 2

3 256 218 68 16 10

4 65536 64594 3904 380 208

5 4.3 X 109 4.3 X 109 3.7 X 107 1,227,756 615,904

LPVD Lecture-11
 Adjustable Device Threshold Voltage
• When one reduces the supply voltage how it affects delay and
performance.

Vdd
td 
(Vdd  Vt ) 2
1 Vt
f max   (1  )(Vdd  Vt )
td Vdd
• When Vdd is closer to Vt, performance decreases rapidly and
becomes limiting factor. Thus one has to scale Vt also.
• But proportionally one can not scale Vt. Because of reduction in
subthreshold current and process variation.

LPVD Lecture-11
 Adjustable Device Threshold Voltage

• One solution is use different Vt devices on the same chip.

• Speed critical devices operate at low Vt while others at
high Vt.

• For this additional mask is needed to identify the low Vt

devices.

• Another method is control Vt by Body bias voltage.

Additional mask is not needed but the Vt stability is poor
and bias voltage generation circuit need additional power.

LPVD Lecture-11
 Assignment
y=a+bc

Use Shannon Decomposition theorem to

find probability and transition density
function.

Submission date 4-4-2011

LPVD Lecture-11
 Assignment

• Draw the 2 input function under P, NP and

NPN equivalence.

• Date of submission 11-4-2011.

LPVD Lecture-11
 Next Topic

• Power optimization techniques at Logic

Level (chapter-5 Yeap)

LPVD Lecture-11