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28-Pseudo Nmos, DCVSL and Dynamic Logic-12!09!2020 (12-Sep-2020) Material I 12-Sep-2020 CMOS Combinational Circuit Design

The document discusses ratioed logic and active load circuits used in CMOS combinational logic design. It describes resistive load, depletion load NMOS, and pseudo-NMOS ratioed logic circuits. It also covers depletion load NMOS and pseudo-NMOS active load circuits. The document then discusses differential cascode voltage switch logic (DCVSL), dynamic logic gates that rely on temporary signal storage on capacitive nodes, and examples of complex logic circuits using dynamic domino logic cascading.

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Parth Vijay
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81 views22 pages

28-Pseudo Nmos, DCVSL and Dynamic Logic-12!09!2020 (12-Sep-2020) Material I 12-Sep-2020 CMOS Combinational Circuit Design

The document discusses ratioed logic and active load circuits used in CMOS combinational logic design. It describes resistive load, depletion load NMOS, and pseudo-NMOS ratioed logic circuits. It also covers depletion load NMOS and pseudo-NMOS active load circuits. The document then discusses differential cascode voltage switch logic (DCVSL), dynamic logic gates that rely on temporary signal storage on capacitive nodes, and examples of complex logic circuits using dynamic domino logic cascading.

Uploaded by

Parth Vijay
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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CMOS Combinational Circuit

Design

Prof. Jagannadha Naidu K


Ratioed Logic
VDD VDD VDD

Resistive Depletion PMOS


Load RL Load VT < 0 Load
VSS
F F F
In1 In1 In1
In2 PDN In2 PDN In2 PDN
In3 In3 In3

VSS VSS VSS


(a) resistive load (b) depletion load NMOS (c) pseudo-NMOS

Goal: to reduce the number of devices over complementary CMOS


Ratioed Logic
VDD

• N transistors + Load
Resistive
Load • VOH = V DD
RL

• VOL = RPN
F RPN + RL

In1 • Assymetrical response


In2 PDN
In3 • Static power consumption

• tpL= 0.69 RLCL


VSS
Active Loads
VDD VDD

Depletion PMOS
Load VT < 0 Load
VSS
F F
In1 In1
In2 PDN In2 PDN
In3 In3

VSS VSS

depletion load NMOS pseudo-NMOS


Pseudo-NMOS VTC
3.0

2.5

2.0 W/L p = 4

1.5
Vout [V]

W/L p = 2
1.0

W/L p = 0.5 W/L p = 1


0.5

W/L p = 0.25
0.0
0.0 0.5 1.0 1.5 2.0 2.5
V in [V]
Differential Cascode Voltage Switch Logic (DCVSL)
V DD V DD

M1 M2

Out Out

A
A
PDN1 PDN2
B
B

VSS VSS
CVSL Inverter
VDD

M1 M3

Z Z

A M2 Ā
M4
  ´
𝑍 = 𝐴 + BC
VDD

Z  A  BC Z  A  BC

A
B
Ā

C B C
XOR with Two Inputs

VDD

A  B( XOR)
A  B( XNOR)

A Ā Ā A

B B
NOR-OR Gate / NAND –AND Gate
Dynamic Logic
 In static circuits at every point in time (except when
switching) the output is connected to either GND or V DD
via a low resistance path.
 fan-in of n requires 2n (n N-type + n P-type) devices

 Dynamic circuits rely on the temporary storage of signal


values on the capacitance of high impedance nodes.
 requires on n + 2 (n+1 N-type + 1 P-type) transistors
Dynamic Gate

Clk Mp Clk Mp
Out Out
In1 CL
A
In2 PDN
C
In3
B
Clk Me
Clk Me

Two phase operation


Precharge (CLK = 0)
Evaluate (CLK = 1)
Dynamic Gate

off
Clk Mp Clk Mp on
1
Out Out
In1 CL ((AB)+C)
A
In2 PDN
C
In3
B
Clk Me
off
Clk Me on

Two phase operation


Precharge (Clk = 0)
Evaluate (Clk = 1)
Conditions on Output
 Once the output of a dynamic gate is discharged, it
cannot be charged again until the next precharge
operation.

 Inputs to the gate can make at most one transition


during evaluation.

 Output can be in the high impedance state during and


after evaluation (PDN off), state is stored on CL
Properties of Dynamic Gates
 Logic function is implemented by the PDN only
 number of transistors is N + 2 (versus 2N for static complementary CMOS)
 Full swing outputs (VOL = GND and VOH = VDD)
 Non-ratioed - sizing of the devices does not affect the logic
levels
 Faster switching speeds
 reduced load capacitance due to lower input capacitance (Cin)
 reduced load capacitance due to smaller output loading (Cout)
 no Isc, so all the current provided by PDN goes into discharging CL
Properties of Dynamic Gates
 Overall power dissipation usually higher than static CMOS
 no static current path ever exists between VDD and GND (including Psc)
 no glitching
 higher transition probabilities
 extra load on Clk
 PDN starts to work as soon as the input signals exceed VTn, so
VM, VIH and VIL equal to VTn
 low noise margin (NML)
 Needs a precharge/evaluate clock
Complex Logic Circuits

VDD

A3 OUT  A0  A1 & A 2  A3 & A 4


A1
A0
A4
A2

VSS
Examples
Dynamic Logic Cascading
Dynamic Logic Cascading
Domino Logic
VDD

precharge OUT
A

NMOS
logic

CLK evaluate

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