William Stallings

Computer Organization
and Architecture
9th Edition

Lecture 1
 Architecture & Organization
• Computer Architecture refers to those attributes of
a system visible to the programmer
—Architecture describes what the computer does.
—Logical Functions(Instruction set, number of bits used for
data representation, I/O mechanisms, techniques for
addressing memory).
• Computer Organization refers to how features are
implemented (Organization describes how it does it.)
— Control signals, interfaces b/w computer and peripherals, memory
technology used.

e.g. -It is an architectural design issue whether a computer will have a

multiply instruction
and -It is an organizational issue whether that instruction will be
implemented by a special multiply unit or by a mechanism that
makes repeated use of the add unit of the system
Ins. Set - complete collection of instructions that are understood by a CPU
Computer Architecture
• Therefore, computer architecture refers to
—Attributes of a system visible to programmers
—Attributes that have a direct impact on the execution
of programs

• Attributes
—Instruction set
—Data representation
—I/O mechanisms
—Addressing techniques
Computer Organization
• Organization refers to operational units and
their interconnections that realize the
architectural specifications.

• Attributes: hardware details transparent to

programmers
—Control signals
—Computer/peripheral interface
—Memory technology
Architecture VS Organization
NO Computer Architecture Computer Organization

Architecture describes Organization describes

1.
what the computer does. how it does it.

Computer Architecture
Computer Organization
deals with functional
2. deals with structural
behavior of computer
relationship.
system.

it deals with high-level it deals with low-level

3.
design issue. design issue.

Where, Organization
Architecture indicates its
4. indicates its
hardware.
performance.
Architecture VS Organization

For designing a computer,

For designing a computer, its
5. organization is decided after its
architecture is fixed first.
architecture.

Computer Architecture is also Computer Organization is

6. called as instruction set frequently called as micro
architecture. architecture.

Computer Architecture
Computer Organization consists
comprises logical functions
of physical units like circuit
7. such as instruction sets,
designs, peripherals and
registers, data types and
adders.
addressing modes.

Architecture coordinates Computer Organization handles

8. between the hardware and the segments of the network in
software of the system. a system.
 Computer Architecture’s Changing Definition

°1950s to 1960s: Computer Architecture Course: Computer

Arithmetic
°1970s to mid 1980s: Computer Architecture Course:
Instruction Set Design, especially ISA (Instruction Set
Architecture) appropriate for compilers
°1990s: Computer Architecture Course: Design of CPU,
memory system, I/O system, Multiprocessors, Networks
°2000s: Multi-core design, on-chip networking, parallel
programming paradigms, power reduction, ARM (Advanced
RISC Machine) Technology
°2010s: Computer Architecture Course: Self adapting systems?
Self organizing structures? DNA Systems/Quantum
Computing?
Architecture & Organization- Family Concept

Many computer manufacturers offer a family of

computer models, all with same architecture but
with differences in organization, i.e.
• All Intel x86 family share the same basic
architecture
• The IBM System/370 family share the same
basic architecture
• Organization differs between different versions
• These newer versions retained the same
architecture so that customer’s software
investment was protected.
Structure & Function
• Structure is the way in which components relate
to each other.
• Function is the operation of individual
components as part of the structure
Computer Functions
• All computer functions are:
—Data processing
—Data storage
—Data movement
—Controlling system
A Functional view of the Computer

The computer system must be

able to process data, store data
and move data b/w itself and
the outside world.

A control unit manages the

computer’s resources and
performance of its functional
parts in response to some
instructions.

This figure depicts the four

possible types of operations.
Operations (1) Data movement

The number of possible

operations that can be
performed …

(1)

The computer can function as a

data movement device, simply
transferring data from one
peripheral or communication
line to another.

e.g. keyboard to
screen
Operations (2) Storage

(2)

The computer can function as a

data storage device, with data
transferred from the external
environment to computer
storage for read/write purpose.

e.g. Internet
download to disk
Operation (3) Processing from/to storage

(3)

This diagram show operations

involving data processing, on
the storage data.

e.g. updating bank

statement
Operation (4)
Processing from storage to I/O

(4)

This diagram show operations

involving data processing, on
data route b/w storage and the
external environment.

e.g. printing a bank

statement
Computer Structure - Top Level

There are four main structural components:

• Central Processing Unit (CPU): Controls the operation of the computer and
performs its data processing functions; often simply referred to as PROCESSOR

• Memory: Stores data

• I/O devices: Moves data b/w the computer and its external environment
• System Interconnection: Some mechanism that provides
for communication among CPU, memory, and I/O devices (Busses).
 Computer Structure - Top Level

Peripherals Computer

Central
Processing Memory
Unit

Computer
Systems
Interconnection

Input
Output
Communication
lines
Structure - The CPU
Control Unit: Controls the operations of the CPU and hence the computer
ALU: Performs the computer’s data processing functions
Registers: Provides storage internal to the CPU
CPU

Computer Arithmetic
Registers and
I/O Logic Unit
System CPU
Bus
Internal CPU
Memory Interconnection

Control
Unit
CPU Interconnection: Some
mechanism that provides for communication
among the control unit, ALU, and registers
Structure - The Control Unit

Control Unit

CPU
Sequencing
ALU Login
Control
Internal
Unit
Bus
Control Unit
Registers Registers and
Decoders

Control
Memory
Overview of a Motherboard
Central Processing Unit
• The CPU or microprocessor performs the following tasks in a
computer system
• Data transfer between itself and the memory or I/O systems
• Simple arithmetic and logic operations
• Program flow via simple decisions
• Although these are simple tasks, but through them, the
microprocessor performs virtually any series of operations or tasks
• Data are operated upon from the memory system or internal
registers.
• Data width are variable and include
• Byte (8-bits)
• Word (16-bits)
• Double word (32-bits)
 Program Concept

• Hardwired Program- process of connecting various components

in desired conf. as a form of programming, the resulting ‘program’ is in
form of hardware, is called a hardwired program- systems are inflexible.
The system accepts data and produces results.

• General purpose hardware- system accepts data and

control signals and produces results (instead of re-wiring hardware for
each new program, supply a new set of
control signals), this new method of Sequence of
programming, a sequence of codes or Data arithmetic and Results
logic functions
instruction is called software.
(a) Programming in
• What is a program? hardware

A sequence of steps Instruction

Instruction interpreter
For each step, an arithmetic or codes
logical operation is done Control signals
For each operation, a different set of Sequence of
control signals is needed Data arithmetic and Results
logic functions
(b) Programming in software
Levels of
Representation
High Level Language temp = v[k];
Program v[k] = v[k+1];
v[k+1] = temp;
Compiler
mov ax, v[k];
Assembly Language Mov bx, v[k+1]
Program
store cx, bx
Assembler int al, 21
0000 1001 sw $15,
1100 0110 1010 1111 4($2)
0101 1000
Machine Language 1010 1111 0101 1000 0000 1001 1100 0110
Program 1100 0110 1010 1111 0101 1000 0000 1001
0101 1000 0000 1001 1100 0110 1010 1111

Machine Interpretation

Control Signal ALUOP[0:3] <= InstReg[9:11] & MASK

Specification
°
°
Computer Components
• The Control Unit and the Arithmetic and Logic
Unit constitute the
—Central Processing Unit
• Data and instructions need to get into the
system and results out
—Input/output
• Temporary storage of code and results, is
needed
—Main memory
Computer Components:
Top Level View
Computer Function- Instruction Cycle
• basic function is execution of a program, which consists of a set of
instructions stored in memory
• each instruction processing (Inst. cycle) consists of two steps:
—1. Fetch Instruction (Fetch Cycle)
- from memory using PC reg. that holds address of inst. to be
fetched next inc PC after each inst fetch, for in sequence
execution of inst, fetched inst. loaded into IR reg.,
—2. Execute this Instruction (Execute Cycle)
- involve several operations, depends on nature of instructions

Machine is
turned off, error
occurs, etc

Instruction Cycle
1. Fetch Cycle
• At beginning, Processor fetches instruction from
memory location pointed to by PC
• Program Counter (PC) holds address of next
instruction to fetch
• Instruction loaded into Instruction Register (IR)
• Increment PC, so that it will fetch next
instruction in sequence

• Processor interprets instruction and performs

required actions (that fall-into 4 categories)
2. Execute Cycle
The processor interprets inst. & performs required actions, that fall
into four categories:
• Processor-memory
—Data transfer between CPU and main memory
• Processor I/O
—Data transfer between CPU and I/O module
• Data processing
—Some arithmetic or logical operation on data
• Control
—Alteration of sequence of operations
—e.g. jump, i.e. fetch an inst from location 49, which
specifies that next inst. be from 82, by setting PC to
82, so next inst is from 82 rather than 50 location
Execution Cycle- An Example

After fetching Obtain instruction from program storage

Inst.

Instruction
Determine required actions and instruction size
Decode
e.g. to add two no.
Operand
Locate and obtain operand data X = Y + Z;
Fetch

Execute Compute result value or status

Result
Deposit results in storage for later use
Store

Next Determine successor instruction;

Instruction
Example of Program Execution

The program fragment shown adds the contents of the memory

word at address 940 to the contents of the memory word at address
941 and stores the result in the latter location:
Example of Program Execution

Instruction 1

Instruction 2

Instruction 3

3 Fetch Cycles 3 Execute Cycles

Instruction Cycle - State Diagram
 Interrupts
• Mechanism by which other modules (e.g. I/O) may interrupt
normal sequence of processing
-provided a way to improve processing efficiency e.g. most external
devices are much slower than processor, causes a very wasteful use of
resources (after each write op, processor must pause and remain idle
until printer catches up)
Some common classes of interrupts are:
• Program- that occurs as a result of an instruction execution
— e.g. arithmetic overflow, division by zero, out of bound memory,
• Timer- this allows OS to perform certain functions on a regular basis
— Generated by internal processor timer
— Used in pre-emptive multi-tasking
• I/O- to signal normal completion of an op or variety of error condition
— from I/O controller
• Hardware failure- caused by a failure
— e.g. a power failure, memory parity error
 Program Flow Control
(a) In User Program Code segments 1, 2, 3 refer to sequences of instructions that don’t involve I/O. The
WRITE calls to an I/O program that is a system utility and that will perform actual I/O operation.

I/O program consists of three sections:

- sequence of instructions, labeled 4, may include

copying data to be output into a special buffer and
preparing parameters for a device command

- actual I/O command, (I/O program must wait for

I/O device to perform requested function)

- a sequences of instructions, labeled 5, to complete

the operation, to indicate the success or failure of
the operation
 Program Flow Control
With interrupts
-processor can be engaged in
executing other instructions while
an I/O operation is in progress
-user program reaches a point at
which it makes a system call in the
form of a WRITE call
-after a few I/O (code & comand)
instructions have been executed,
control returns to the user
program, meanwhile external
device is busy accepting data from
computer memory and printing it.
-this I/O operation is conducted
concurrently with execution of
inst. in user program
-to accept more data from
processor, I/O module sends an
interrupt request signal to
processor, the processor responds
by suspending operation of current
user program
Interrupt Cycle

• Added to instruction cycle

• Processor checks for interrupt
— Indicated by an interrupt signal
• If no interrupt, fetch next instruction
• If interrupt pending:
— Suspend execution of current program
— Save context
— Set PC to start address of interrupt handler routine
— Process interrupt
— Restore context and continue interrupted program
Transfer of Control via Interrupts
Instruction Cycle with Interrupts
Program Timing
Short I/O Wait
Instruction Cycle (with Interrupts) -
State Diagram
Multiple Interrupts
• Disable interrupts
—Processor will ignore further interrupts whilst
processing one interrupt
—Interrupts remain pending and are checked after first
interrupt has been processed
—Interrupts handled in sequence as they occur
• Define priorities
—Low priority interrupts can be interrupted by higher
priority interrupts
—When higher priority interrupt has been processed,
processor returns to previous interrupt
Multiple Interrupts - Sequential
Multiple Interrupts – Nested
Time Sequence of Multiple Interrupts
Interconnection Structures
• Collection of paths connecting various modules is called
interconnection structure
• As computer consists of a set of components or modules
of three basic types i.e.,
—Processor (CPU)
—Memory
—Input/Output
Computer Modules input and output for each module type

1) Memory module:
-consists of N words of equal length
-each word is assigned a unique numerical address
(0, 1, ….N-1)
-a word of data can be read from or written into
memory
-nature of op is indicated by read, write control
signals, location is specified by an address
2) I/O module:
-similar to memory module, two op read and write
-I/O module may control more than one external
device, each interface is called port with unique
address
3) Processor module:
-reads in inst and data, writes out data after
processing, uses control signals to control overall
op of system. It also receives interrupt signals
Memory Connection (module)
• Receives and sends data
• Receives addresses (of locations)
• Receives control signals
—Read
—Write
—Timing
Input/Output Connection (module)
• Similar to memory from computer’s viewpoint
• Output
—Receive data from computer
—Send data to peripheral
• Input
—Receive data from peripheral
Input/Output Connection (module)
• Receive control signals from computer
• Send control signals to peripherals
—e.g. spin disk
• Receive addresses from computer
—e.g. port number to identify peripheral
• Send interrupt signals (control)
CPU Connection (processor module)
• Reads instruction and data
• Writes out data (after processing)
• Sends control signals to other units
• Receives (& acts on) interrupts
Buses
• There are a number of possible interconnection
systems
• Single and multiple BUS structures are most
common
• e.g. Control/Address/Data bus (PC)
• e.g. Unibus (DEC-PDP), PCI
What is a Bus?
• A communication pathway connecting two or more devices
• It is a shared transmission medium
• Multiple devices connect to bus
• Only one device at a time can successfully transmit
• e.g. an 8-bit unit of data can be transmitted over eight bus lines
• Computer systems contains a number of different buses that
provide pathways b/w components at various levels of computer
system hierarchy.
System Bus
• A bus that connects major computer components (processor,
memory, I/O) is called a system bus
Bus Structure
• A system bus consists of from about 50 to hundreds of separate
lines, each line is assigned a particular meaning or function
• Commonly the bus lines can be classified into three functional
groups i.e. data lines, address lines and control lines.
Data Bus data lines collectively called data bus

• Carries data or Provide a path for moving data

b/w system modules
• Data bus may consists of from 32 to hundreds
of separate lines
• no. of lines being referred to as Width of data
bus, each line carry 1-bit, so no. of lines
determined how many bits can be transferred at
a time, i.e. Width is a key determinant of
performance
• If data bus is 8-bits wide, each inst is 16-bits
long, then processor must access memory
module twice during each instruction cycle
Address Bus
• Identify the source or destination of data on the
data bus
• e.g. if processor needs to read a word of data
from memory, it puts address of desired word
on address bus.
• Bus width of address bus determines maximum
memory capacity of system
• Address bus are also used to address I/O ports
Control Bus
• are used to control the access to and use of data and
address lines
• Control lines transmit both command and timing info
b/w system modules, timing signals indicate validity of
data and address info, command signals specify
operations to be performed, e.g.
— Memory write signal (causes data on bus to be written into
addressed location)
— Memory read signal (causes data from addressed location to
be places on bus)
— I/O read/write signal, Transfer ACK
— Bus request (a module needs to gain control of the bus)
— Bus grant (module has been granted control of the bus)
— Interrupt request (indicates that an interrupt is pending)
— Clock signals (used to synchronize operations)
— Reset (initialize all modules)
Bus Interconnection Scheme
• What do buses look like?
—Parallel lines on circuit boards
—Ribbon cables
—Strip connectors on mother boards
– e.g. PCI (peripheral component interconnect)
—Sets of wires
Single Bus Problems
• Lots of devices on one bus leads to:
—Propagation delays
– Long data paths mean that co-ordination of bus use can
adversely affect performance
– Bus may become a bottleneck, If aggregate data transfer
demand approaches the capacity of bus
• Most systems use multiple buses to overcome
these problems
Traditional Bus Arch. (with cache)
• I/O transfers to and from main
memory across system bus don’t
interfere with processor’s activity
• An expansion bus interface
buffers data transfers b/w system
bus and I/O controllers on
expansion bus, and allows system
to support a wide variety of I/O
devices
• It is reasonably efficient but
begins to break down as higher an
higher performance is seen in I/O
devices

SCSI = Small computer system interface

High Performance Bus Architecture

• It requires only a bridge

b/w processor’s bus &
high-speed bus

• A local bus connects

processor to a cache
controller, which in turn
connected to a system bus
that supports memory

• Cache controller is
integrated into a bridge,
or buffering device, that
connects to the high speed-
bus
Elements of Bus Design

There are a few basic parameters or design elements that

serve to classify and differentiate buses:
Elements of Bus Design
1) Bus Types
• Dedicated (permanently assigned to one function)
—Separate data & address lines
—Potential advantage is high throughput
• Multiplexed (using same lines-bus for multiple purpose)
—Address and data information may be transmitted
over same set of lines, using
—Address valid or data valid control line
— Advantage - fewer lines, saves space and cost
— Disadvantages
– More complex control circuit is needed within each module
– Ultimate performance, a potential reduction in performance
because certain events that share same lines cannot take
place in parallel
2) Bus Arbitration
• More than one module may need control of the bus
• e.g. an I/O module may need to read/write directly to
memory, without sending data to processor, because
• Only one module may control bus at one time,
• So some method of arbitration is needed
• Arbitration may be centralised or distributed
Centralised Arbitration
• A single hardware device is responsible for
allocating time on the bus, i.e.
—Bus Controller
—Arbiter
• May be part of processor or separate module
Distributed Arbitration
• There is no central controller
• Each module may claim the bus
• Each module contains access control logic and
modules act together to share the bus
 3) Timing
• A way in which events are coordinated on bus
• Synchronous timing or asynchronous timing
• Synchronous timing
—Occurrence of Events on bus is determined by a clock
—Bus includes a clock line upon which a clock transmits a
regular sequence of 1s and 0s of equal duration,
—A signal 1-0 is called a bus cycle or a time slot
—All other devices on the bus can read clock line
—Usually sync on leading edge i.e. (all events start at
beginning of a clock cycle)
—Usually a single cycle for an event
Synchronous Timing Diagram
- e.g. processor places a
memory address on address
lines during first clock cycle,
and may assert various status
lines (1st cycle)
- processor issues an address
enable signal (1st cycle)
- for read op processor issues
a read command at 2nd cycle
- a memory module validate
address, after a delay of one
cycle, places data on data bus
- for write op processor puts
data on data bus at start of
2nd cycle, and issues write
command, then memory
module copies data from
data bus during 3rd clock
 Asynchronous Timing – Read Diagram

-Occurrence of one event on bus follows and depends on occurrence of a previous event.
e.g. processor places address and status signals on bus, after pausing for these signals to
stabilize it issues read command, memory module decodes address & places data on data
bus, and then asserts ACK to signal processor that data available. After reading data,
processor de-asserts read signal, this cause memory module to drop data and ACK lines,
finally processor removes address information
 Asynchronous Timing – Write Diagram

- Synch timing is simpler to implement and test, but less flexible than Asynch. Because
all devices are tied to fixed clock rate, system cannot take advantage of advances in
device performance, but with Asynch a mixer of slow-fast devices, using older-newer
tech. can share bus
4) Bus Width

4) Data Transfer Type

Bus supports various data transfer types:
- Write (non-multiplexed) operation
- Read (multiplexed) operation
- Read (non-multiplexed) operation
- Read-modify-write operation
- Read-after-write operation etc.
PCI Bus
• Peripheral Component Interconnection is a popular
high-bandwidth or peripheral bus
• Use of up to 64 data lines at 66 MHZ, for a raw transfer
rate of 528 MBytes/s
• It is high-speed supports other buses attached to it, as
well as designed to meet economically I/O requirements
of modern systems
• support a variety of microprocessor-based
configurations, including both single- and multiple-
processor systems
• It makes use of synchronous timing and a centralized
arbitration scheme
PCI Bus Lines Structure (required)
PCI (32 or 64-bit bus), contains 49 signal lines and are
divided into following functional groups:
• Systems lines or pins
—Including clock and reset
• Address & Data pins
—32 time mux lines for address/data
—Interrupt & validate lines
• Interface Control (Control the timing of transactions and provide
coordination among initiators and targets)
• Arbitration
—Not shared
—Direct connection to PCI bus arbiter
• Error lines (report parity and other errors)
PCI Bus Configuration…
PCI Bus Configuration…
Problem 3:
Problem 1:
Foreground Reading
• Stallings, chapter 3 (all of it)
• www.pcguide.com/ref/mbsys/buses/

• In fact, read the whole site!

• www.pcguide.com/