Harvard & Von Neumann (Princeton) Architecture
HARVARD & PRINCETON ARE THE UNIVERSITIES OF UNITED STATE.
VON NEUMANN IS THE SCIENTIST NAME IN PRINCETON UNIVERSITY.
Harvard Architecture: -
Program & data memory are separate.
Can fetch the next instruction when current
Instruction is in execution.
Von Neumann (Princeton) Architecture: -
Memory interface unit is responsible for access
of memory space between reading & passing
data between register.
Memory interface unit is the bottle neck unit.
Adv: -
1. Simplify to design the processor.
2. Content of memory can be used for variable
Storage & program storage.
RISC & CISC Architecture
RISC: REDUCED INSTRUCTION SET COMPUTERS.
In RISC instruction are bare as minimum possible to allow the user to design
its own application. (We can say that 8085 is RISC processor)
Ex: - MOV B,A
LDA 2000 H
MUL B (First transfer the data from B to A, then Multiply)
CISC: COMPLEX INSTRUCTION SET COMPUTERS.
In CISC processor there tends to be large number of instructions, each carrying
out a different permutation of the same operations. (We can say that 8086 is CISC
processor)
Ex: - MUL AX, BX (Direct Multiplication can take place)
In general it is observed that RISC are faster then CISC. But, there are some CISC
processor which are faster then RISC. i.e. we cannot say always that this one is
faster.
General definitions of microcomputers
Microcomputer is at the lowest end of the
computer range in terms of speed and storage
capacity. Its CPU is a microprocessor. The most
common application of personal computers (PC)
is in this category. The PC supports a number of
input and output devices. Examples of
microcomputer are IBM PC, PC-AT
Introduction to Micro controller
A microcontroller is a single chip unit which, though having limited
computational capabilities, possesses enhanced input-output
capabilities and a number of on-chip functional units. Particularly
suited for use in embedded systems for real-time control
applications. with on-chip program memory and devices. Common
peripherals include serial communication devices, timers, counters,
pulse width modulators, analog-to-digital and digital-to-analog
converters. Enables single-chip system implementation and hence
smaller and lower-cost products.
Examples: Motorola 68HC11xx, HC12xx, HC16xx, Intel 8051,
80251, PIC 16F84, PIC18, ARM9, ARM7, Atmel AVR etc
Microprocessor v/s Microcontrollers
Microcontroller
A microcontroller (also microcomputer, MCU or µC) is a small computer on a
single integrated circuit consisting internally of a relatively simple CPU, clock,
timers, I/O ports, and memory. Microcontrollers are designed for small or
dedicated applications. Thus, in contrast to the microprocessors used in personal
computers and other high-performance or general purpose applications
Microprocessor
A microprocessor incorporates most or all of the functions of a computer's
central processing unit (CPU) on a single integrated circuit. The first
microprocessors emerged in the early 1970s and were used for electronic
calculators, using binary-coded decimal (BCD) arithmetic on 4-bit words. Other
embedded uses of 4- and 8-bit microprocessors. Affordable 8-bit microprocessors
with 16-bit addressing also led to the first general purpose microcomputers in the
mid-1970s
Embedded Vs External Memory Devices
Embedded Devices (Microcontroller): -
1. 8051 Microcontroller
2. AVR Microcontroller
3. PIC Microcontroller
4. ARM Microcontroller
External Memory Devices (Microprocessor): -
1. 8085 Microprocessor
2. 8086 Microprocessor
3. 80186 Microprocessor
4. 80286 Microprocessor
5. 80386 Microprocessor
Evolution of Processor
4004:
4-bit microprocessor. 4KB main memory.
45 instructions. PMOS technology. 50 KIPS
8008: (1971)
8-bit version of 4004. 16KB main memory.
48 instructions. NMOS technology.
8080: (1973)
8-bit microprocessor. 64KB main memory.
2 microseconds clock cycle time; 500,000 instructions/sec. 10X faster than 8008.
8085: (1977)
8-bit microprocessor - upgraded version of the 8080, 64KB main memory, 1.3
microseconds clock cycle time; 769,230, instructions/sec, 246 instructions, Intel sold 100
million copies of this 8-bit microprocessor.
8086: (1978) 8088 (1979)
16-bit microprocessor, 1MB main memory, 2.5 MIPS (400 ns).
4- or 6-byte instruction cache, Other improvements included more registers and additional
instructions.
80286: (1983)
16-bit microprocessor very similar in instruction set to the 8086.
16MB main memory, 4.0 MIPS (250 ns/8MHz).
8085 architecture and its operation
Signal descriptions and pins of 8085
Signal descriptions and pins of 8085
Control is provided by a variety of lines which support memory and I/O interfacing,
requiring only a 5 volt supply.
The 8085 comes in two models, the 8085A and the 8085A-2. The 8085A expects clock
frequency of 3 MHz, while the 8085A-2 expects clock frequency of 5 MHz. This clock is
generated by a crystal externally.
The 8085 make use of multiplexing of the lower 8 bits of the address with the data bits on
the same 8 pins. This requires that the external circuitry be able to catch and hold the A0-
A7 lines for later use.
The upper 8 bits of the address have their own pins, however.
The General Purpose Register Array contains the B, C, D, E, H, and L registers, each 8
bits wide. The B and C, D and E, and H and L registers may be grouped into 16-bit
register pairs. The H & L register pair may be used to store indirect addresses.
An address generation system consisting of the Program Counter, Stack Pointer, address
latches, and incremented / decremented.
The array also contains the Program Counter (PC) and Stack Pointer (SP). These 16-bit
registers contain the address of the next instruction part to be fetched, and the address of
the top of the stack, respectively.
STATUS FLAG REGISTER
The Status Flags of the 8085 indicate the logical conditions that existed as a result of the
execution of the instruction just completed.
SZxACxPxC
ZERO FLAG: This flag is set to a 1 by the instruction just ending if the A Register
contains a result of all 0’s.Otherwise 0.
SIGN FLAG: This flag is set to a 1 by the instruction just ending if the leftmost, bit of
the A Register is set to a 1. Otherwise 0.
PARITY FLAG: This flag is set to a 1 by the instruction if the A Register is left with an
even number of bits set on, i.e., in even parity. Otherwise 0.
CARRY FLAG: This flag is set to a 1 by the instruction just ending if a carry out of the
leftmost bit occurred during the execution of the instruction. Otherwise 0.
AUXILIARY CARRY FLAG: This flag is set to a 1 by the instruction just ending if a
carry occurred from bit 3 to bit 4 of the A Register. Otherwise 0.
Timing and control unit
Timing Diagram is a graphical representation. It
represents the execution time taken by each
instruction in a graphical format. The execution
time is represented in T-states.
One byte, two byte and three byte instruction
Instruction Cycle: The time required to execute an
instruction. (Fetch cycle + Execution cycle)
Machine Cycle: The time required to access the
memory or input/output devices .
T-State: Subdivision of operation performed in one
clock cycle. The machine cycle and instruction cycle
takes multiple clock cycles.
Timing and control unit
The 8085 microprocessor has following machine cycles.:
1. Op-code Fetch cycle(4T or 6T).
2. Memory read cycle (3T)
3. Memory write cycle(3T)
4. I/O read cycle(3T)
5. I/O write cycle(3T)
6. Interrupt Acknowledge cycle(6T or 12T)
Timing and control unit
Timing diagram
Instruction of 8085: -
DATA TRANSFER: -
1. MOV r1, r2 Move contents of register (A, B, C, D, E, H, L) r2 to r1.
Eg. MOV A, B Move the contents of B to A
2. MVI r, data Move the data to the specify register
Eg. MVI C, F0H Move the data F0 to the reg C
3. LDA 2000H Load the contents of memory location 2000 to Accu. A
4. LXIH 2000H Load the 20 to H Load the 00 to L
5. MOV A, M Load the value of data from mem location 2000 to A.
6. MOV M, A Load the value of A to the memory pointed by HL pair.
7. MVI M, F0H Load F0 to the memory pointed by HL pair.
8. STA 2000H Store the data of Accu. A to the memory 2000H
9. LHLD 2000H Data of 2000 to L, Data of 2001 to H
10. SHLD 2000H Store the value of L to 2000 & H to 2001
11. LDAX D If DE=2000H, then load the value of 2000 to Accu. A
12. STAX D if DE=3000H, Store the value of A to the 3000H
13. XCHG Exchange the value of DE with HL pair.
ARITHMETIC: -
1. ADD C A+C=A
2. ADD M A+[H-L]=A
3. ADI F0H A+F0=A
4. ADC C A+C+[CF]=A
5. ADC M A+[H-L]+[CF]=A
6. ACI F0H A+F0+[CF]=A
7. DAD D H-L+D-E=H-L
8. SUB B A-B=A
9. SUB M A-[H-L]=A
10. SUI F0H A-F0=A
11. SBB B A-B-[CF]=A
12. SBB M A-[H-L]-[CF]=A
13. SBI F0H A-[F0]-[CF]=A
14. INR D Increment the content of D by one
15 INX D Increment the content of DE pair by one
16. DCR L Decrement the content of L by one.
17. DCR H Decrement the content of HL pair by one.
LOGICAL GROUP: -
1. ANA D Logical AND Between the contents of A and D
2. AND M Logical AND Between the contents of A and [H-L]
3. ANI F0 H Logical AND Between the contents of A and F0 H
4. ORA C Logical OR Between the contents of A and C
5. ORA M Logical OR Between the contents of A and [H-L]
6. ORI F0 H Logical OR Between the contents of A and F0 H
7. XRA C Logical XOR Between the contents of A and C
8. XRA M Logical XOR Between the contents of A and [H-L]
9. XRI 0F H Logical XOR Between the contents of A and 0F H
10. CMA Complement the contents of A only.
11. CMC Complement the carry status.
12. STC Set the carry flag.
13. CMP D Compare the contents of A and D. i.e. A-D. But the contents of
A and D are not changed.
14. CMP M Compare the contents of A and [H-L]. i.e. A-[HL]. But the
contents of A and [HL] are not changed.
15. CPI F0 H Compare the contents of A and F0. i.e. A-F0. But the contents
of A and F0 are not changed.
16. RLC Rotate Accu. Left.
17. RRC Rotate Accu. Right
18. RAL Rotate Accu. Left through carry.
19. RAR Rotate Accu. right through carry.
BRANCH GROUP: -
Unconditional
1. JMP 2000 Jump to the location 2000
2. CALL 2000 Jump to the location 2000
Conditional
1. JZ 2000 Jump to the location 2000 if there is zero in result i.e. in Accu.
2. JNZ 2000 Jump to the location 2000 if there is non zero in result i.e. in Accu.
3. JC 2000 Jump to the location 2000 if there is carry in result i.e. in Accu.
4. JNC 2000 Jump to the location 2000 if there is no carry in result i.e. in Accu.
5. JP 2000 Jump to the location 2000 if result is positive in Accu.
6. JM 2000 Jump to the location 2000 if result is negative in Accu.
7. JPE 2000 Jump to the location 2000 if result contain even parity in Accu.
8. JPO 2000 Jump to the location 2000 if result contain odd parity in Accu.
9. RET Return from the subroutine.
10. PUSH C Push the contents of C reg. into stack.
11. POP D Retrieve the contents of stack top into reg C.
12. HLT End of the program.
13. NOP No operation.
OPCODE FORMAT
Registered code Register pair code
B 000 BC 00
C 001 DE 01
D 010 HL 10
E 011
H 100
L 101
M 110
A 111
ADDRESSING MODES
Immediate Addressing Mode:-
The data to be used is given in the instruction itself. Immediate addressing mode instruction
are either 2 byte or 3 byte long.
EX. MVI A, 20H ADI 30H LXI H, C200H
Register addressing mode
This mode of addressing specify the register or register pair that contain the data.
EX. MOV A, B ADD B
Direct addressing mode
In this mode the operand is given by a direct address where the data is present. The direct
addressing mode instruction is a 3 byte inst.
EX. LDA 2000H STA 2000H
Indirect Addressing Mode
Here Inst. Does Not Have Address Of The Data. But The Instruction Point Where The Address
Is Stored
EX. MOV A, M MOV M, A
Implied or inherent addressing mode
This mode does not required any operand. The data is specified within the opcode itself.
EX. RAL RAR
INSTRUCTION TYPE
The first part of the instruction is called opcode and the second part is called operand. The operand may be
either 8 bit data or memory location. Depending upon the number of bytes required to specify an
operation the instruction are of 3 bytes.
ONE BYTE INSTRUCTION:-
A 1 byte instruction include the opcode and the operand in the 8 bits only i.e. One byte
MOV A, B
MOV A, C
ADD B
TWO BYTE INSTRUCTION:-
The 2 byte instruction uses first byte to specify the operation and second byte to specify the operand.
MVI A, 20
MVI B, 30
THREE BYTE INSTRUCTION:-
The 3 byte instruction uses first byte to specify the operation, second and third bytes are used to specify
the operand. Generally those instruction are used to specify memory address.
LDA ADDRESS
LDA 2000H
INSTRUCTION TYPE
The first part of the instruction is called opcode and the second part is called operand. The operand may be
either 8 bit data or memory location. Depending upon the number of bytes required to specify an
operation the instruction are of 3 bytes.
ONE BYTE INSTRUCTION:-
A 1 byte instruction include the opcode and the operand in the 8 bits only i.e. One byte
MOV A, B 01 111 000 = 78H
MOV A, C 01 111 001 = 79H
ADD B 1000 0 000 = 80H
TWO BYTE INSTRUCTION:-
The 2 byte instruction uses first byte to specify the operation and second byte to specify the operand.
MVI A, 20 0011 1110 0010 0000
MVI B, 30 0000 0110 0011 0000
THREE BYTE INSTRUCTION:-
The 3 byte instruction uses first byte to specify the operation, second and third bytes are used to specify
the operand. Generally those instruction are used to specify memory address.
LDA ADDRESS
LDA 2000H 0011 1010 0010 0000 0000 0000
INSTRUCTION SET
DATA TRANSFER OPERATION
This group of instruction copies data from source to destination
MOV A, B MOV A, M MVI R, DATA LDA 2000H LXI H 2000H
LHLD 2000H LDAX 2000
ARITHEMATIC OPERATION
This group of instruction perform arithematic operation like addition subtraction
ADD R ADD M ADC D ADC M ADI F0
DAD R INR R INX H DCR R DCX H
LOGICAL OPERATION
This group of instruction perform logical operation such as and, or, not etc
ANA R ANA M ANI DATA ORA R
XRA R CMACMP R RAL
BRANCH OPERATION
This group of instruction change the path of program execution or sequence.
a) CONDITIONAL b) UNCONDITIONAL
JC ADD. JNC ADD. CALL ADDRESS
JZ ADD. JNZ ADD JMP ADDRESS
STACK AND MACHINE OPERATION
This group of instruction perform stack and machine control function.
PUSH R POP R NOP HLT
To find the addition of
two eight bit numbers
sum is 8 bits.
LXIH 2501 H ADDITION OF TWO 8-BIT NUMBER, SUM
MOV A,M 16 BITS
INX H
ADD M LXI H,2501H
STA 2503 H MVI C,00
HLT MOV A,M
INX H
ADD M
To find the subtraction of JNC
two eight bit numbers
INR C
STA 2503H
LXIH 2501 H
MOV A,M
MOV A,C
INX H STA 2504H
SUB M HLT
INX H
MOV M,A
HLT
DECIMAL ADDITION OF TWO 8-BIT Decimal substraction of two 8-bit
NUMBER ; SUM 16-BITS number
LXI H,2501H LXI H,2501H
MVI C,00 MVI C,00
MOV A,M MOV A,M
INX H
INX H
SUB M
ADD M DAA
DAA JNC AHEAD
JNC AHEAD INR C
INR C AHEAD STA 2503H
AHEAD STA 2503H MOV A,C
STA 2504H
MOV A,C
HLT
STA 2504H
HLT
To shift an 8-bit number to left by
ADDITION OF 2 16 BIT two bits
NUMBER. SUM IS 16 BIT OR
MORE. LXIH 2501 H
LHLD 2501 H MOV B,M
XCHG MOV A,M
LHLD 2503 H ADD B
MVI C, 00 H
ADD B
STA 2502 H
DAD D
HLT
JNC HEAD
INR C To shift an 16 bit number left by
HEAD SHLD 2505 H two bit
MOV A, C
STA 2507 LHLD 2501
HLT DAD H
DAD H
SHLD 2503
HLT
To mask off 4 LSB's of To mask ON 4 LSB's of 8 bit
8 bit number number
LDA 2501 LDA 2501 H
H ORI 0F H
ANI F0 H STA 2502 H
STA 2502 H HLT
HLT
To mask ON 4 MSB's of 8 bit
To mask off 4 MSB's of number
8 bit number
LDA 2501 LDA 2501 H
H ORI F0 H
ANI 0F H STA 2502 H
STA 2502 H HLT
HLT
To find the largest of two numbers
WAP in 8085 to add 16 bit LXIH 2500
data 1234H & 4321H. MOV A, M
MVI B, 12 H INX H
MVI C, 34 H MVI CMP M
D, 43 H MVI E, JNC HEAD
21 H MOV A, E MOV A, M
ADD C MOV HEAD STA 2502
L, A MOV A, D HLT
ADC B To find the smallest of two numbers
MOV H, A LXIH 2500
MOV A, M
HLT
INX H
CMP M
JC HEAD
MOV A, M
HEAD STA 2502
HLT
To find the smallest number in data array from 2501 to 2509.
Total no. are 8. and the count is stored in 2500.
LXIH 2500 H
MOV C,M
INX H
MOV A,M
DCR C
BACK INX H
CMP M
JC LOOP
MOV A,M
LOOP DCR C
JNZ BACK
STA 2450 H
HLT
Register B=75 H is interpreted as packed BCD. Unpack the BCD
digit and save them in D & E REGISTER.
PACKED BCD = XY UNPACKED BCD1 = 0X, BCD2 = 0Y
MVI B, 75 H
MOV A, B
ANI F0 H
RRC
RRC
RRC
RRC
MOV D, A
MOV A, B
ANI 0F
MOV E, A
HLT
Techniques for I/O Interfacing
Memory-mapped I/O
Peripheral-mapped I/O
Memory-mapped I/O
8085 uses its 16-bit address bus to identify a
memory location
Memory address space: 0000H to FFFFH
8085 needs to identify I/O devices also
I/O devices can be interfaced using addresses
from memory space
8085 treats such an I/O device as a memory
location
This is called Memory-mapped I/O
Peripheral-mapped I/O
8085 has a separate 8-bit addressing scheme for
I/O devices
I/O address space: 00H to FFH
This is called Peripheral-mapped I/O or I/O-
mapped I/O
