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8086 Architectute 1

The document discusses the origin and evolution of microprocessors from the 1930s to present day. It describes the transition from mechanical calculating devices to vacuum tubes to transistors which enabled the development of integrated circuits and early microprocessors in the 1960s and 1970s. The document then summarizes the five generations of microprocessors, highlighting important processors from each generation like the 4004, 8086, 80386 and more recent 64-bit processors. It also discusses microprocessor architecture, programming advancements, the 8086 architecture including its functional blocks, registers and memory segments.

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DILITH DINESH

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0% found this document useful (0 votes)

62 views50 pages

8086 Architectute 1

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DILITH DINESH

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Microprocessor and Interfacing

01/03/23
Origin of Microprocessors
 Microprocessor is the greatest invention of the 20th Century
 Evolution started from the earlier mechanical calculating devices-In
1930
 In 1950-Replaced by Vacuum tubes-Replaced by transistors
 Transistor Technology led to the introduction of minicomputer in
the 1960s and the PC revolution in the 1970s
 TT led to the development of complex devices called ICs

01/03/23
Origin of Microprocessors
 MPU later evolved as an IC and was designed to fetch instructions
and execute the predefined arithmetic and logic functions.
 Intel was the 1st MPU producer and has been holding a large share
of the world market for this product.
 Evolution of the microprocessor is categorized into five generations.
 First generation (1971-1973)
 Referred to as the first generation systems.
 Processed Instruction serially

01/03/23
Origin of Microprocessors-First generation(1971-
1973)

 1st microprocessor-4004-introduced in 1971

 4-bit 4004 microprocessors ran at 108kHz and contained 2300
transistors
 Fabrication using p-channel MOS tech.
 low cost, slow speed and not compatible with TTL
 In 1972, Intel made 8-bit 8008 and 8080 µP.

01/03/23
Origin of Microprocessors-Second
generation(1974-1978)
 It marked the beginning of very efficient 8-bit µP.
 Some of the popular processors were Motorola’s 6800 and 6809,
Intel’s 8085, Zilog’s Z80.
 2nd generation devices- use of newer semiconductor tech to
fabricate chips.
 By using n-channel (NMOS) tech.
 Advantages: Five-fold increase in instruction execution speed and
higher chip densities.

01/03/23
Origin of Microprocessors-Third
generation(1978-1980)
 3rd generation as dominated by Intel’s 8086 and Zilog’s Z8000.
 16-bit processors with minicomputer-like performance
 Tech of 16-bit arithmetic and pipelined instruction
 IC transistor counts- 250,000
 Example:Motorola’s MC68020-On chip cache was incorporated for
the first time and pipeline was increased to five or more stages.
 Design techniques-HMOS tech.
 Advantages:
 Speed-power product is four times better than that of the NMOS.
 Can accommodate twice the circuit density of NMOS.

01/03/23
Origin of Microprocessors-Fourth
generation(1981-1995)
 4th generation designs contains more than a million transistor
in a single package.
 Beginning of 32-bit µP’s.
 Intel 80386 and Motorola 68020/68030 were introduced
 Fabrication-High density/High speed CMOS(HCMOS)

01/03/23
Origin of Microprocessors-Fifth generation(1995-
till date)
 It employs decoupled super scalar processing.
 Design contains more than 10 million transistors
 Introduction of an on-chip functionalities
 High speed memory I/O devices, intro of 64-bit µP’s
 Intel lead the show here with Pentium, Celeron, Dual-and quad-
core and very recently i3,i5,i7 working with up with up to 3.33 GHz
Turbo Boost speed.

01/03/23
01/03/23
Applications

• The microprocessor has made possible the

– inexpensive hand-held electronic calculator, the digital wristwatch, and the
electronic game.
• Microprocessors are used to control consumer electronic devices,
such as the
– programmable microwave oven and videocassette recorder;
– to regulate gasoline consumption and antilock brakes in automobiles;
– to monitor alarm systems; and to operate automatic tracking and
– targeting systems in aircraft, tanks, and missiles and to control radar arrays
that track and identify aircraft, among other defense applications.

01/03/23
Programming Advancements

 Once programmable machines developed, programs and

programming languages began to appear.
 Stored in the computer memory system as groups of instructions
called a program
 Mathematician John von Neumann first modern person to develop a
system to accept instructions and store them in memory
 UNIVAC -early 1950s, assembly language was used to simplify
entering binary code.
 Assembler allows programmer to use mnemonic codes…
 such as ADD for addition
 In place of a binary number.
 such as 0100 0111
 Assembly language an aid to programming

01/03/23
8086-Microprocessor Architecture

 In 1978, Intel released its first 16-bit microprocessor-8086.

 It executes the instructions at 2.5MIPS
 Execution time for one instruction is 400ns(1/MIPS).
 8086 can address 1MB(1MB=220 bytes) of memory-20 bit
address bus
 Width of the data bus is 16bits
 Feature- Small six-byte instruction queue
 Instruction fetched from the memory are placed before they are
executed.

01/03/23
8086-Microprocessor Architecture
 Functional block diagram of 8086, subdivided into the following
two units:
1. Execution unit (EU)
2. Bus interface unit (BIU)
Execution unit: It includes the ALU, eight 16-bit general purpose
registers, a 16-bit flag register, and a control unit
Bus Interface unit: It includes an adder for address calculations,
four-16 bit segment registers(CS,DS,SS,ES), a 16-bit instruction
pointer(IP), a six-byte instruction queue, and bus control logic

01/03/23
8086-Microprocessor Architecture
 Components in BIU:
 Segment Register
 The Instruction pointer
 Address generation Register
 Bus control logic
 Instruction Queue

 Components in EU:
 Arithmetic logic Unit: ALU
 Status and control logic
 General purpose registers
 Temporary operand registers

01/03/23
8086-Microprocessor Architecture


01/03/23
General Purpose Registers

15 8 7 0
AX AH AL Accumulator

BX BH BL Base
Data Group
CX CH CL Counter

DX DH DL Data

SP Stack Pointer

BP Base Pointer
Pointer and
Index Group
SI Source Index

DI Destination Index

01/03/23
General Purpose Registers

 General Purpose registers can be used to store 8-bit or 16-bit data

during program execution. In addition each register has the
following function:
 AX/AL:
 It is used as a accumulator.
 It is used in the multiply,divide, and input/output operations, and in some
decimal and ASCII adjustment instructions.
 BX:
 It holds the offset address of a location in the memory. It is also used to refer to
the data in the memory using the look-up table technique, with the help of the
XLAT (Translate )instruction.

01/03/23
General Purpose Registers

 CX/CL:
 CX is used to hold the count value while executing the repeated string
instruction and the LOOP instruction. (REP/REPE/REPNE).
 CL- Used to hold the count value while executing the shift/rotate
instructions.
 DX:
 Used to hold a part of the result during a multiplication operation and a
part of the dividend before a division operation.
 Used to hold the I/O device address while executing the IN and OUT
instructions.
 Offset: This is a 16-bit number that is added to the base address
of a segment, to select a byte of instruction or data from the
memory

01/03/23
General Purpose Registers

SP:
 Stack Pointer is used to hold the offset address of the data stored at the top of the stack segment.
 SP is used along with the SS register to decide the address at which the data is to be pushed or popped, during
the execution of the PUSH or POP instruction, respectively.
BP:
 BP register is called base pointer
 Used to hold the offset address of the data to be read from or written into the stack segment.
SI:
 Source index register
 Used to hold the offset address of the source data in the data segment, mainly useful while executing string
instructions.
DI:
 Destination index register
 Used to hold the offset address of the destination data in the data or extra segment, mainly useful while
executing string instructions

01/03/23
Segment registers

 Segment refers to a portion of the memory

 Function of these registers is to indicate the starting or base address of the code segment,
data seg, stack seg, extra seg respectively in the memory.
 CS contains Instruction of a program, DS-Data of a program,
SS holds the stack of the program, w hich is needed while executing the CALL and RET
instructions and also to handle interrupts, ES is an additional data segment
 Data, code or stack for a program is stored
 In 8086, the max size of a segment can be 64KB

 A segment always begins at a memory address divisible by 16.

Eg: CS(64K(MAX) (20000H-2FFFFH), Total(1MB)(00000H-FFFFFH)

01/03/23
Segment registers and default offset registers in the 8086

Segment registers Default offset registers

CS IP

DS BX,SI,DI, 8-or 16-bit

displacement

SS SP and BP

ES DI for string instruction

01/03/23
Segmented Memory

01/03/23
Address Calculation

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01/03/23
Flag Register
 A flag is a flip-flop which indicates some condition produced by
the execution of an instruction, or controls certain opertions of
the EU.

01/03/23
01/03/23
01/03/23
A trap is an
Flag Register exception in a user
process. It's caused
by division by zero
or invalid memory
access.
It's also the usual
way to invoke a
kernel routine (a
system call)
because those run
with a higher
priority than user
code.
Handling is
synchronous (so
the user code is
suspended and
Interrupt(Time delay) continues
TF= 1; 8086 gets interrupt TF=0; No interrupt afterwards).

01/03/23
Flag register
S – sign flag: 1- result of any computation is negative.
For signed computations, the sign flag equals to the MSB of the result.
Z – zero flag : 1 – result of the computation or comparision performed by instruction is zero.
P – Parity flag : 1 – if the lower byte of the result contains even number of 1s.
C – Carry Flag: it is set when there is a carry out of MSB in the case of addition or a borrow in the case of
subtraction.
T – Trap flag: if this flag is set, the processor enters the single step execution mode. In other words, a trap
interrupt is generated after execution of each instruction
I – Interrupt flag: if this flag is set, the maskable interrupt are recognized by the CPU, otherwise they are
ignored.
Direction flag: used by string manipulation instructions.
0 – the string is processed beginning from the lowest address to highest address. (autoincrementing mode).
1 – the string is processed beginning from the highest address to lowest address. (autodecrementing
mode).
AC – Auxiliary carry flag: it is set if there is carry/borrow from lowest nibble during addition / subtraction.
O – Overflow flag: it is set, if overflows occurs.

01/03/23
Flag Register
 Examples
Sign Flag:
+13=00001101
+9 =00001001
+22=00010110 (Sign bit is 0; so result is positive)

+13=00001101
-9 =11110111 (2’s complement for -9 with sign bit
+4=100000100(Ignore Carry; Sign bit is 0 so result is positive)

+9 =00001001
-13=11110011 (2’s complement for -13 with sign bit
-4 = 11111100 sign bit is 1; negative)
00000011 Invert each bit
1( add 1)
00000100( -4; magnitude)

01/03/23
Flag Register
Note: Range of Signed Numbers that can be represented with 8 binary bits;
In normal codes, the range is 0 to +127 and from -1 to -128
Note: 01111111 +127
.
.
00000001 +1
00000000 Zero
11111111 -1
.
.
10000001 -127
10000000 -128

01/03/23
Flag Register
 If register AL=7FH and the instruction ADD AL,1
 Result:
 AL = 80H ; 7FH+1=80H
 CF = 0 ; No carry out of bit 7
 PF = 0 ; 80H has an odd no of logic 1’s
 AF = 1 ; Carry out of bit 3 into bit 4
 ZF = 0 ; Result is not 0
 SF = 1 ; Bit 7 is set
 OF = 1 ; Result(+128) exceeds the capacity of register AL

01/03/23
Internal Arch of 8086
 8086 has two blocks BIU and EU. The BIU performs all bus operations such as
instruction fetching, reading and writing operands for memory and calculating
the addresses of the memory operands. The instruction bytes are transferred to
the instruction queue.
 EU executes instructions from the instruction system byte queue.
 Both units operate asynchronously to give the 8086 an overlapping instruction
fetch and execution mechanism which is called as Pipelining. This results in
efficient use of the system bus and system performance.
 BIU contains Instruction queue, Segment registers, Instruction pointer, Address
adder.
 EU contains Control circuitry, Instruction decoder, ALU, Pointer and Index
register, Flag register.

01/03/23
Internal Arch of 8086
BUS INTERFACE UNIT:
 It provides a full 16 bit bidirectional data bus and 20 bit address bus.
 The bus interface unit is responsible for performing all external bus operations.
Specifically it has the following functions:
Instruction fetch, Instruction queuing, Operand fetch and storage, Address relocation and
Bus control.
 The BIU uses a mechanism known as an instruction stream queue to implement a
pipeline architecture. This queue permits prefetch of up to six bytes of instruction code.
When ever the queue of the BIU is not full, it has room for at least two more bytes and
at the same time the EU is not requesting it to read or write operands from memory,
the BIU is free to look ahead in the program by prefetching the next sequential
instruction.
 These prefetching instructions are held in its FIFO queue. With its 16 bit data bus, the
BIU fetches two instruction bytes in a single memory cycle.
 After a byte is loaded at the input end of the queue, it automatically shifts up through
the FIFO to the empty location nearest the output

01/03/23
Internal Arch of 8086
 The EU accesses the queue from the output end. It reads one instruction byte
after the other from the output of the queue. If the queue is full and the EU is not
requesting access to operand in memory.
 These intervals of no bus activity, which may occur between bus cycles are
known as Idle state.
 If the BIU is already in the process of fetching an instruction when the EU request
it to read or write operands from memory or I/O, the BIU first completes the
instruction fetch bus cycle before initiating the operand read / write cycle.
 The BIU also contains a dedicated adder which is used to generate the 20bit
physical address that is output on the address bus. This address is formed by
adding an appended 16 bit segment address and a 16 bit offset address.
 For example: The physical address of the next instruction to be fetched is
formed by combining the current contents of the code segment CS register and
the current contents of the instruction pointer IP register.
 The BIU is also responsible for generating bus control signals such as those for
memory read or write and I/O read or write.
01/03/23
Internal Arch of 8086
EXECUTION UNIT :
 The Execution unit is responsible for decoding and executing all instructions. The EU
extracts instructions from the top of the queue in the BIU, decodes them, generates
operands if necessary, passes them to the BIU and requests it to perform the read or write
bus cycles to memory or I/O and perform the operation specified by the instruction on the
operands.
 During the execution of the instruction, the EU tests the status and control flags and
updates them based on the results of executing the instruction.
 If the queue is empty, the EU waits for the next instruction byte to be fetched and shifted
to top of the queue.
 When the EU executes a branch or jump instruction, it transfers control to a location
corresponding to another set of sequential instructions.
 Whenever this happens, the BIU automatically resets the queue and then begins to fetch
instructions from this new location to refill the queue.