Multiplexer

The multiplexer or MUX is a digital switch, also called as data selector. It is a Combinational Logic Circuit
with more than one input line, one output line and more than one select line. It accepts the binary
information from several input lines or sources and depending on the set of select lines, a particular input
line is routed onto a single output line.

4x1 Multiplexer has four data inputs I3, I2, I1 & I0, two selection lines s1 & s0 and one output Y. The block
diagram of 4x1 Multiplexer is shown in the following figure.
One of these 4 inputs will be connected to the output based on the combination of inputs present at these
two selection lines. Truth table of 4x1 Multiplexer is shown below.
VHDL CODE:
 
architecture rtl of MUX is
library IEEE;
begin
use IEEE.std_logic_1164.all;
with s select
use IEEE.std_logic_arith.all;
Y<= I(0) when "00",
use IEEE.std_logic_unsigned.all;
I(1) when "01",
 
I(2) when "10",
entity MUX is
I(3) when others;
port(
end rtl;
I: in std_logic_vector (3 downto 0);
S: in std_logic_vector (1 downto 0);
Y: out std_logic);
end MUX;
 
TEST BENCH: stim : process
 entity testbench is begin
-- empty  
end testbench; i <= "1100";
 architecture tb of testbench is s <="00";
 -- DUT component wait for 20 ns;
component MUX is  s <="01";
port(I: in std_logic_vector (3 downto 0); wait for 20 ns;
S: in std_logic_vector (1 downto 0);  
Y: out std_logic); s <="10";
end component; wait for 20 ns;
signal i: std_logic_vector (3 downto 0); s <="11";
signal s: std_logic_vector (1 downto 0); wait for 20 ns;
signal y: std_logic;  
Begin wait;
uut : MUX port map(i=> i,s=> s,y=> y); end process;
end tb;
 
 
 Demultiplexer

De-Multiplexer is a combinational circuit that performs the reverse operation of Multiplexer. It has
single input, ‘n’ selection lines and maximum of 2  outputs. The input will be connected to one of
n

these outputs based on the values of selection lines.

Since there are ‘n’ selection lines, there will be 2n possible combinations of zeros and ones. So, each
combination can select only one output. De-Multiplexer is also called as De-Mux
-- Simple demux design
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity demux is
port(
I,S1,S0 : in std_logic;
O1,O2,O3,O4 : out std_logic);
End demux;

architecture rtl of demux is

begin

O1 <= I and (not s0) and (not s1);

O2 <= I and (not s0) and s1;
O3 <= I and s0 and (not s1);
O4 <= I and s0 and s1;
end rtl;
 begin
-- Testbench for demux uut : demux port map(
library IEEE; i=> i,s0=> s0,s1=> s1,O1 => O1,O2 => O2, O3 => O3, O4 => O4);
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all; stim: process
use IEEE.std_logic_unsigned.all; begin
I <= '1';
entity testbench is s0 <='0';
-- empty s1 <='0';
end testbench; wait for 20 ns;
architecture tb of testbench is s0 <='0';
s1 <='1';
-- DUT component wait for 20 ns;
component demux is s0 <='1';
port (I, S0,S1 :in std_logic; s1 <='0';
O1,O2,O3,O4 :out std_logic); wait for 20 ns;
end component; s0 <='1';
s1 <='1';
wait for 20 ns;
-- Connect DUT wait;
end process;
signal I,s1,s0,O1,O2,O3,O4 : std_logic;
end tb;