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System Tasks and Compiler Directives

This document discusses system tasks and compiler directives in Verilog. It describes various system tasks for displaying information like $display, monitoring signals like $monitor, and stopping/finishing simulations like $stop and $finish. It also lists common format specifiers for $display. Finally, it briefly introduces the most common compiler directives like `define, `include, `ifdef, and `timescale which control Verilog compilation.

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Soumyadeep Das
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545 views12 pages

System Tasks and Compiler Directives

This document discusses system tasks and compiler directives in Verilog. It describes various system tasks for displaying information like $display, monitoring signals like $monitor, and stopping/finishing simulations like $stop and $finish. It also lists common format specifiers for $display. Finally, it briefly introduces the most common compiler directives like `define, `include, `ifdef, and `timescale which control Verilog compilation.

Uploaded by

Soumyadeep Das
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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System Tasks

And Compiler
Directives
System
Tasks
Verilog provides standard system tasks for certain
routine operations.
All system tasks appear in the form $<keyword>.
Operations such as displaying on the screen,
monitoring values of nets, stopping, and finishing
are done by system tasks.
2
Displaying Information

$display is the main system task for displaying


values of variables or strings or expressions.
Usage: $display(p1, p2, p3,....., pn);

Tuesday, February 2, 20XX Sample Footer Text 3


String Format Specifications
Format Display
%d or %D Display variable in decimal
%b or %B Display variable in binary
%s or %S Display string
%h or %H Display variable in hex
%c or %C Display ASCII character
%<special charter> Display special character
Display hierarchical name (no
%m or %M
argument required)
4
Format Display
%v or %V Display strength
%o or %O Display variable in octal
%t or %T Display in current time format
Display real number in scientific
%e or %E
format (e.g., 3e10)
Display real number in decimal
%f or %F
format (e.g., 2.13)
Display real number in scientific or
%g or %G
decimal, whichever is shorter
5
Monitoring Information
 Verilog provides a mechanism to monitor a signal
when its value changes. This facility is provided
by the $monitor task.
 Usage: $monitor(p1,p2,p3,....,pn);
 Only one monitoring list can be active at a time. If
there is more than one $monitor statement in your
simulation, the last $monitor statement will be the
active statement. 6
 Two tasks are used to switch monitoring on and off.
Usage: $monitoron;
$monitoroff;
 Example:
initial
begin
$monitor($time, " Value of signals clock = %b ,
reset = %b", clock,reset);
end 7
Stopping and finishing in a simulation
The task $stop is provided to stop during a simulation.

Usage: $stop;

The $finish task terminates the simulation.

Usage: $finish;

8
Example:
initial
begin
clock = 0; reset = 1;
#100 $stop;
#900 $finish;
end
9
Compiler Directives
Compiler directives specifies how a compiler should
process it inputs.
It controls the compilation of Verilog description.
A directive is effective from the point at which it is
declared to the point where another directive
overrides it.
10
Types of Compiler Directives
The most used compiler directives in Verilog are:
`define :The `define directive is used to define text
macros in Verilog
`include :The `include directive allows you to
include entire contents of a Verilog source file in
another Verilog file during compilation.
The other 2 directives being- `ifdef and `timescale.
11
Thank You

12

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