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Modules and Ports

Modules define reusable components in Verilog. They contain ports that provide the interface for communication. Ports must be declared and connected properly between a module definition and instantiation. Inputs must be nets internally and can be nets or regs externally. Outputs must be nets internally and externally. Width matching and connection order rules must also be followed for legal port connections.

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Soumyadeep Das
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60 views20 pages

Modules and Ports

Modules define reusable components in Verilog. They contain ports that provide the interface for communication. Ports must be declared and connected properly between a module definition and instantiation. Inputs must be nets internally and can be nets or regs externally. Outputs must be nets internally and externally. Width matching and connection order rules must also be followed for legal port connections.

Uploaded by

Soumyadeep Das
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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MODULES AND PORTS

BY- SAYANI DATTA


MODULE
S
• Modules are defined with the keyword
module.
• The module name, port list, port declarations,
and optional parameters must come first in a
module definition.
• The five components within a module are:
variable declarations, dataflow statements,
instantiation of lower modules, behavioural
blocks, and tasks or functions.
• The endmodule statement must always come
last in a module definition.
• Verilog allows multiple modules to be
defined in a single file.
• All components except module, module
name, and endmodule are optional and can
be mixed and matched as per design needs.
PORTS
• Ports / terminals provide the interface by which a
module can communicate with its environment.
LIST OF PORTS
module fulladd4(sum, c_out, a,b,c_in)
output [3:0]sum;
output c_out;
input [3:0]a,b;
input c_in;
.
<module internals>
.
endmodule
 module fulladd4(sum, c_out, a, b, c_in);

 module Top;
PORT DECLARATIONS
• All ports in the list of ports must be declared in
the module.
• output sum, c_out;
• input a,b,c_in;
PORT CONNECTIONS RULES

• Inputs: Internally, input ports must always be of


the type net. Externally, the inputs can be
connected to a variable which is a reg or a net.
• Outputs: Internally, outputs ports can be of the
type reg or net. Externally, outputs must always
be connected to a net. They cannot be
connected to a reg.

• Inouts: Internally, inout ports must always be


of the type net. Externally, inout ports must
always be connected to a net.
• Width matching: It is legal to connect internal
and external items of different sizes when
making intermodule port connections. However,
a warning is typically issued that the widths do
not match.
• Unconnected ports: Verilog allows ports to
remain unconnected.

Example:

fulladd4 fa0(SUM, , A, B, C_IN);


ILLEGAL PORT CONNECTIONS
module Top;
//Declare connection variables
reg [3:0]A,B;
reg C_IN;
reg [3:0] SUM;
wire C_OUT;
//Instantiate fulladd4, call it fa0
fulladd4 fa0(SUM, C_OUT, A, B, C_IN);
BY ORDERED LIST
• The signals to be connected must appear in the
module instantiation in the same order as the
ports in the port list in the module definition.
BY NAME
• Verilog provides the capability to connect
external signals to ports by the port names, rather
than by position.
HIERARCHICAL NAMES
• A hierarchical name is a list of identifiers
separated by dots (".") for each level of hierarchy.
• Hierarchical name referencing allows us to denote
every identifier in the design hierarchy with a
unique name.
THANK YOU

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