CHAPTER 2:

BASIC ARCHITECTURE OF THE 8088 AND 8086

MICROPROCESSORS
Under this chapter we will learn:-
 Internal architecture of the 8086/8088 microprocessors
 Memory address space and data organization
 Data types
 Segment registers and memory segmentation
 Pointer and index register
 Status and flag register and
 The Stack

1 Mr. Abdisa L. AUWC dept of CS

Internal architecture of the 8086/8088 microprocessors
Concepts important to the internal operation of
8088/8086.
It ha the following 2 concepts:
1. Pipelining
2. Registers
 Pipelining
 Two ways to make CPU process information faster:
 Increase the working frequency – technology dependent
 Change the internal architecture of the CPU
 Pipelining is to allow CPU to fetch and execute at the same
time

2 Mr. Abdisa L. AUWC dept of CS

 Intel implemented the concept of pipelining by splitting the internal
structure of the 8088/8086 into two sections that works
simultaneously:
 Execution Unit (EU) – executes instructions previously
fetched
 Bus Interface Unit (BIU) – accesses memory and peripherals

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 The BIU contains the following registers:
 IP , CS, DS, SS and ES
 The EU contains the following 16-bit registers:
 AX , BX , CX, DX, SP, BP, SI and DI
 The ALU performs all basic computational operations:
arithmetic, logical, and comparisons.
 The control unit orchestrates the operation of the other units.
 It fetches instructions from the on-chip cache, decodes them, and
then executes them.
 Each instruction has the control unit direct the other function units
through a sequence of steps that carry out the instruction's intent .

4 Mr. Abdisa L. AUWC dept of CS

 Inside The 8088/8086…registers
 Registers AX
16-bit register
 To store information temporarily AH AL
8-bit reg. 8-bit reg.

Category Bits Register Names

General 16 AX, BX, CX, DX
8 AH, AL, BH, BL, CH, CL, DH, DL
Pointer 16 SP (stack pointer), BP (base pointer)
Index 16 SI (source index), DI (destination index)
Segment 16 CS (code segment), DS (data segment)
SS (stack segment), ES (extra segment)
Instruction 16 IP (instruction pointer)
Flag 16 FR (flag register)
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 Anatomy of a Register

Extended Register
Word Register

Bits 16-31 Bits 8-15 Bits 0-7

High Byte Low Byte

Register Register

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 General Registers
32 bit Registers 16 bit Registers 8 bit Registers

EAX EBP AX BP AH AL

EBX ESI BX SI BH BL

ECX EDI CX DI CH CL

EDX ESP DX SP DH DL
Bits 16-31 Bits 8-15 Bits 0-7

7 Mr. Abdisa L. AUWC dept of CS

The 32-bit general-purpose registers EAX, EBX, ECX,
EDX, ESI, EDI, EBP, and ESP are provided for holding
the following items: operands for logical and arithmetic
operations, operands for address calculations, and memory
pointers.
Registers can be broken down into 16 and 8 bit registers.
We will use the notation “(E)AX” to refer to any of AL,
AH, AX, or EAX.
Each of the lower two bytes of the EAX, EBX, ECX, and
EDX registers can be referenced by the names AH, BH,
CH, and DH (high bytes) and AL, BL, CL, and DL (low
bytes).
The lower two bytes of the other registers – EBP, ESI,
EDI, and ESP – can not be referenced.

8 Many instructions
Mr. Abdisa assign specific registers to hold
L. AUWC dept of CS
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 General Registers I
• EAX – ‘Accumulator’
• accumulator for operands and results data
• usually used to store the return value of a procedure

• EBX – ‘Base Register’

• pointer to data in the DS segment

• ECX – ‘Counter’
• counter for string and loop operations

• EDX – ‘Data Register’

• I/O pointer

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 General Registers II
• ESI – ‘Source Index’
• source pointer for string operations
• typically a pointer to data in the segment pointed to
by the DS register
• EDI – ‘Destination Index’
• destination pointer for string operations
• typically a pointer to data/destination in the
segment pointed to by the ES register

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 General Registers III
• EBP – ‘Base Pointer’
• pointer to data on the stack
• points to the current stack frame of a procedure

• ESP – ‘Stack Pointer’

• pointer to the top address of the stack
• holds the stack pointer and as a general rule should
not be used for any other purpose

13 Mr. Abdisa L. AUWC dept of CS

 Segment Registers
CS – ‘Code Segment’
 contains the segment selector for the code segment where
the instructions being executed are stored
DS(ES,FS,GS) – ‘Data Segment’
 contains the segment selectors for the data segment where
data is stored
SS – ‘Stack Segment’
 contains the segment selector for the stack segment, where
the procedure stack is stored

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Memory Segment is used to store the memory
addresses of instructions and data.
 Memory Organization.
 Each byte in memory has a 20 bit address starting
with 0 to 220-1 or 1 Meg of addressable memory.
 Addresses are expressed as 5 hex digits from
00000 – FFFFF.

1. Problem: But 20 bit addresses are TOO BIG to fit

in 16 bit registers?
Solution: Memory Segment.
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• Block of 64K (65,536) consecutive memory
bytes.
• A segment number is a 16 bit number.
• Segment numbers range from 0000 to FFFF.
• Within a segment, a particular memory
location is specified with an offset.
• An offset also ranges from 0000 to FFFF

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 Memory Model for 20-bit Address Space

17 Mr. Abdisa L. AUWC dept of CS

 Question: how to generate memory address?
Ans: Physical address = segment
address*10+offset address

Example: we have segment no 6020h

and offset is 4267h then
60200+4267=64467h  physical
address.

18 Mr. Abdisa L. AUWC dept of CS

 Flag Register
• Flag Register (status register)
– 16-bit register
– Conditional flags: CF, PF, AF, ZF, SF, OF
– Control flags: TF, IF, DF

ZF
 The EFLAGS Register I
Carry Flag – CF (bit 0)
 Set if an arithmetic operation generates a carry or a
borrow out of the most-significant bit of the result;
cleared otherwise.
Parity Flag – PF (bit 2)
 Set if the least-significant byte of the result
contains an even number of 1 bits; cleared otherwise.
Adjust Flag – AF (bit 4)
 Set if an arithmetic operation generates a carry or a
borrow out of bit 3 of the result; cleared otherwise.

20 Mr. Abdisa L. AUWC dept of CS

 The EFLAGS Register II
Zero Flag – ZF (bit 6)
 Set if the result is zero; cleared otherwise
Sign Flag – SF (bit 7)
 Set equal to the most-significant bit of the result,
which is the sign bit of a signed integer
Overflow Flag – OF (bit 11)
 Set if the integer result is too large a positive
number or too small a negative number (excluding the
sign-bit) to fit in the destination operand; cleared
otherwise

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 Instruction Pointer
EIP
‘Instruction Pointer’
Contains the offset within the code segment of the next
instruction to be executed
Cannot be accessed directly by software

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 The Stack
The stack starts in high memory and grows toward low
memory

ESP
Current
stack
frame stack
EBP
Caller’s growth
stack
frame

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 Stack
A section of RAM memory used by the CPU to store
information temporarily.

• Registers: SS (Stack Segment) and SP (stack Pointer)

• Operations: PUSH and POP

– PUSH – the storing of a CPU register in the
stack
– POP – loading the contents of the stack back
into the CPU

• Logical and offset address format: SS:SP

24 Mr. Abdisa L. AUWC dept of CS