How to Create the Parts?

(Layout, Design Rules, and Stick Diagram)

Taufiq Alif Kurniawan, ST, MT, M.Sc.Eng Departemen Teknik Elektro, Universitas Indonesia [email protected]
4/22/12

Lectureredit Master subtitle style Click to 3

Introduction

Reading

W&H 3 3 Layout Design Rules W&H 3.3 Layout Design Rules W&H 6.1-6.2.2 Layout parasitics +W&H 3.6 Advanced layout rules

Introduction

In this lecture we look at the effect that fabrication constraints have on the layout we need to 4/22/12 produce For this class we will use a

Geometric Design Rules

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Layer
Fabrication

uses a set of layers that are not natural for a designer:

Some of these layers are really the combination of layers a designer would like to think about. For example active is really all the diffusion layers merged together. Many of these layers can be derived from other layers. For example the selects 4/22/12 the threshold adjust and

Layer Choice

The layers a designer uses is set by the technology files

These tell the tools what to do Allow the tools to handle many different technologies

Dominant

layout editor is

Virtuoso

Dominant layout tool used in the industry

4/22/12 Can handle very complex layout

SCMOS Design Rules Highlights

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Stick Diagram
We

represent the different wiring layers with different colors

Wires on the same layer that 4/22/12 touch ALWAYS connect. There is

Basic Layout Planning

Here

are a few simple guidelines to CMOS layouts

You need to route power and ground (in metal)
No

one will auto connect it for you.

Try to keep nMOS devices near nMOS devices and pMOS devices near pMOS devices near pMOS devices.
So

nMOS usually are placed near Gnd, and pMOS near Vdd
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Transistor Rules
CMOS

transistors are generally defined by at least four physical masks

Active (diffusion, diff or thinox)

all

areas where either n- or p-type diffusion is to be placed, or where the gates of transistors are to be placed.

n-select (n-implant, nimp or n+) p-select (p-implant, pimp or n+)

What

type of diffusion required. n-select 4/22/12 surrounds active regions where n-type

Transistor Rules (contd)

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Contact and Metal Rules

There

are several available contacts:

Metal to p-active (p-diffusion) Metal to n-active (n-diffusion) Metal to polysilicon Metal to well or subsrate

generally

Metal

rules may be complicated by varying spacing dependent on width : as the width increases, the spacing increases. Metal 4/22/12

Via Rules
Vias

are normally of uniform size within layer. They may increase in size toward the top of a metal stack. For instance, large vias required on power busses are constructed from an array uniformly sizes vias. Other Rules
Differing

nMOS and pMOS gate

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lengths

MOSIS design rule options

SUBM rules are somewhat more conservative than SCMOS rules, DEEP rules are even more conservative.

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MOSIS design rule

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MOSIS design rule (contd)

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MOSIS design rule (contd)

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MOSIS design rule (contd)

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An Example

Choose global directions for routing layers Position power lines in top/bottom layer of metal
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An Example Step 2

Cluster together NMOS with NMOS and PMOS with PMOS Generally keep gate orientation the same 4/22/12

An Example Step 3

Arrange transistors so that common gates line up

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An Example Step 4

Connect everything up
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Convert to real layout

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Fabrication is more complex than that

As

technology has scaled, design rules have become complex

Problem is we are running into physics limitations

We

are creating features smaller than the wavelength of light steps have their own constraints

Processing The

following slides talk about 4/22/12 some of these issues The

Metal Density

Old rule: minimum metal density For Al, metals were etched away

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Antenna Rules

Reactive ion etch charges up metal lines Charge can accumulate and zap a gate oxide If a gate sees a long metal before a diffusion does

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CMOS Process Enhancements Silicon on Insulator

Process where the transistors are fabricated on an insulator. Two main insulators are used, SiO2 and sapphire. Advantage : elimination of the capacitance between the source/drain regions and body, leading to higher-speed devices.

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CMOS Process Enhancements

High-k

Gate Dielectrics

MOS transistors need high gate capacitance to attract charge to the channel very thin SiO2 gate dielectrics. C = .A/d Gate leakage will be unacceptably large in such thin gates. Gates could use thicker dielectrics and hence leak less if a material with higher dielectric constant were available. 4/22/12

CMOS Process Enhancement

Higher

Mobility

Increasing the mobility of the semiconductor improves drive current and transistor speed, this has been achieved by using silicon germanium (SiGe) for bipolar transistors. SiGe can be constructed on conventional CMOS processing by adding a few extra implantation steps.
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Circuits Elements
Capacitors

The most common capacitor used in CMOS processes today is the MIM (metal-insulator-metal) that is normally placed between metal layers n and n-1 (n is normally the top level metal layer) to minimize the stray capacitance of the bottom plate. Another type of capacitor that is possible in scaled processes is the 4/22/12 fringe (or fractal) capacitor, which is

Circuits Elements (contd)

Capacitor

1-4 fF/um2

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High-Q Very linier Highvalued capacito r with low

Circuits Elements (contd)

Resistors

Resistor can be built from any layer, with final resistance depending on the resistivity of the layer. Building large resistances in a small area requires layers with high resistivity, particularly polysilicon and diffusion. Another material used for highquality resistors is nichrome need a special4/22/12 steps. proc.

Circuits Elements (contd)

Resistor

Mean der struct ure

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Circuits Elements (contd)

Inductors

The most common monolithic inductor is the spiral inductor, which is a spiral upper-level metal. The parameters of interest to a designer are its inductance, the Q of the inductor, and self-resonant frequency. High Q low phase-noise osc, narrow filters and low-loss circuits. Q-values 4/22/12 for typical planar inductors

Circuits Elements (contd)

Inductor

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Power and Delay : A Gates Metrics

When

we use a gate we care about its logic function

That is the desired output

It

also consumes resources that care about

Delay
The

output becomes valid some time after inputs settle

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Power

R and C is All You Need

Delay

can be estimated by simple RC models can be estimated (mostly) from C alone to do either, we need to have a R, C model of gates

Power But

And the wires And the wires

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Resistance? Capacitance?
Resistance

Relates current to voltage (V = IR) Measures how easy it is for current to flow (Actually weird relates a force qV/L to a velocity) Relates charge to voltage (Q = CV) Exists between any two conductors
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Capacitance

Resistance
Resistance

of a conductor

Resistivity r * Length/Area Designer does not control r, t Generally deal with r/t Called ohm/square (Rsq)

Thats

why LONG wires have higher resistances

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Transistor Resistance
For

transistors
and L

Designer chooses
W

Wider

transistor

More current Lower R

is a surrogate for

1/Ids
4/22/12 R depends on Vdd

Rules of Thumb for Resistance

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Capacitance and Delay

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Load Capacitance
Cload

comes from three factors:

Gate capacitance of driven transistors. Diffusion capacitance of source/drain connected to the wire. Wire capacitance 3. Wire capacitance

Today,

a 1u technology is the really cheap technology that students 4/22/12 use and advanced

Real Wires

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Rules of Thumb for Capacitance

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Since The Tool Has The Layout

Let

it estimate the resistance and capacitance

Can compute more accurate numbers

But

it only can do this when the layout is complete

Which is why the simple models are still useful

If

you know the wires is going to 4/22/12 be 10mm

Even Better
Let

someone else do the design

Use their cells

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Homework 1
1.

Consider the design of a CMOS compound OR-OR-AND-INVERT (OA122) gate computing F=(A+B).(C+D).
a.

Sketch a transistor-level schematic Sketch a stick diagram Estimate the area from the stick diagram Layout your gate with a CAD tool using unit-sized transistors (optional) Compare the layout size to the estimated area Consider

b.

c.

d.

e.

2.

A carry lookahead adder computes G=G3+P3(G2+P2(G1+P1G0)). designing a compound gate to compute G.

a.

Sketch a transistor-level schematic Sketch a stick diagram Estimate the area from the stick diagram Layout your gate with a CAD tool using unit-sized transistors (optional)

b.

c.

d.

e.

4/22/12 Compare the layout size to the estimated area