Digital Logic

Progammable
Standard Logic ASICs Full Custom
Logic Devices

Microprocessor
SPLDs CPLDs FPGAs & RAM

TTL CMOS Gate Standard

74xx 4xxx Arrays Cells

Acronyms
SPLD = Simple Prog. Logic Device
PAL = Prog. Array of Logic
CPLD = Complex PLD
FPGA = Field Prog. Gate Array
ASIC = Application Specific IC
 Programmable Logic Devices
• FPLD (Field-Programmable Logic Device)
• Supplied with no predetermined logic function
• Programmed by user to implement any digital
logic function
• Require specialized computer software for
design and programming.
• Implementation of digital circuits with low cost
and low risk.
• Technology of choice for low to medium volume
products (say hundreds to few 10’s of thousands
per year).
• Good and low cost design softwares.
 Programmable Logic Devices
• SPLDs (Simple PLDs)
– ROM, PLA or PAL
– Small gate count, fixed internal routing, deterministic
propagation delays
• CPLDs
– Multiple SPLDs onto a single chip
– Programmable interconnect
• FPGAs
– An array of logic blocks
– Large number of gates, user selectable interconnection,
delays depending on design and routinig
– A high ratio of flip-flops to logic resources
 Simple PLD Types
• 􀁻 ROM (Read Only Memory)
􀁺 Fixed AND plane
Programmable OR plane
• 􀁻 PLA (Programmable Logic Array)
Programmable AND plane
Programmable OR plane
• 􀁻 PAL (Programmable Array Logic)
Programmable AND plane
Fixed OR plane
 Programmablility
For all kinds of PLDs
• 􀁻 One Time Programmable (OTP)
• 􀁻 Re-Programmable (RP)
SPLD Structure
 ROM, PALs and PLAs
• Pre-fabricated building block
x1 x2 xn of many AND/OR gates (or NOR,
NAND)

•"Personalized" by making or
Input buffers breaking connections among
and the gates
Inverters

x1 x1 xn xn
P1
P2
Output inverters
AND plane OR plane
Pk

f1 fm
 Array-Based Programmable
Logic
I5 I4 I3 I2 I1 I0 Programmable
OR array I3 I2 I1 I0 Programmable
OR array I5 I4 I3 I2 I1 I0 Fixed OR array

Programmable AND array Fixed AND array Programmable AND array

O 3O 2O 1O 0 O3O2O1O0 O 3O 2O 1 O 0

PLA PROM PAL

Indicates programmable connection
Indicates fixed connection
 Programming a PROM
1 X2 X1 X0

: programmed node
NA NA f 1 f 0
 All possible connections are available
before programming

A B C

F0 F1 F2 F3
A B C

Unwanted connections are "blown"

AB

/BC

A /C

/B /C

F0 F1 F2 F3

Note: some array structures

work by making connections
rather than breaking them
 PLA Before
programming

A B C D

AB PLA After programming

AB
F0 = A B + A' B'
CD F1 = C D' + C' D
CD

F0 F1
 Difference between Programmable Array Logic (PAL) and
Programmable Logic Array (PLA):

PAL : AND array programmable

OR array fixed

A given column of the OR array has access to only a subset

of the possible product terms
Design Example: BCD to Gray
Code Converter
Truth Table

A B C D W X Y Z
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 1 1 1 0
0 1 1 0 1 0 1 0
0 1 1 1 1 0 1 1
1 0 0 0 1 0 0 1
1 0 0 1 1 0 0 0
1 0 1 0 X X X X
1 0 1 1 X X X X
1 1 0 0 X X X X
1 1 0 1 X X X X
1 1 1 0 X X X X
1 1 1 1 X X X X
 A A
AB AB
CD 00 01 11 10 CD 00 01 11 10

00 0 0 X 1 00 0 1 X 0

01 0 1 X 1 01 0 1 X 0
D D
11 0 1 X X 11 0 0 X X
C C
10 0 1 X X 10 0 0 X X

B B
K-map for W K-map for X

A A
AB AB
CD 00 01 11 10 CD 00 01 11 10

00 0 1 X 0 00 0 0 X 1

01 0 1 X 0 01 1 0 X 0
D D
11 1 1 X X 11 0 1 X X
C C
10 1 1 X X 10 1 0 X X

B B
K-map for Y K-map for Z

Minimized W=A+BD+BC
Functions: X = B C'
Y=B+C
Z = A'B'C'D + B C D + A D' + B' C D'
A B C D
A
BD
BC

0
BC
0
0
0
B
C
0
0
ABCD
BCD
AD
BCD

W X Y Z
 \A \A
A 1
\B
4
\C
B D
2 3 W
D
B
C 3
B 2 D
C 4 4 Z
A
5
B D 1 \D
22 1 X \B
C 1
C 3
\C \D

1: 7404 hex inverters

2 Y
B 1 2,5: 7400 quad 2-input NAND
\B 3: 7410 tri 3-input NAND
4: 7420 dual 4-input NAND

Code Converter Discrete Gate Implementation

4 SSI Packages vs. 1 PLA/PAL Package!
 Example: Magnitude Comparator
A B C D

ABCD

A A
ABCD
AB AB
CD 00 01 11 10 CD 00 01 11 10 ABCD
00 1 0 0 0 00 0 1 1 1
ABCD
01 0 1 0 0 01 1 0 1 1
D D
AC
11 0 0 1 0 11 1 1 0 1
C C
10 0 0 0 1 10 1 1 1 0 AC

B B BD
K-map for EQ K-map for NE
BD
A A
AB AB
ABD
CD 00 01 11 10 CD 00 01 11 10
00 0 0 0 0 00 0 1 1 1 BCD

01 1 0 0 0 01 0 0 1 1 ABC
D D
11 1 1 0 1 11 0 0 0 0
C C
BCD
10 1 1 0 0 10 0 0 1 0

B B
K-map for LT K-map for GT
Transistor-Level Structure
PAL 16 L 8
 PAL
Architecture
• Recall the PAL device
we studied earlier
• PAL16L8
– 16 inputs
– 32 input AND gates
– up to 8 output functions
• Outputs are selectable
between OR/NOR
PAL 16 R4
PAL Programmer
 PLA table

Equations Product Inputs Outputs

term A B C F0 F1 F2 F3
F0 = A + B' C' AB 1 1 - 0 1 1 0
F1 = A C' + A B Reuse
F2 = B' C' + A B BC - 01 0 0 0 1
of
F3 = B' C + A AC 1 - 0 0 1 0 0
terms
BC - 00 1 0 1 0
A 1 - - 1 0 0 1

Input Output Side:

Side:
1 = asserted in term 1 = term connected to output
0 = negated in term 0 = no connection to output
- = does not participate
 Design Example
• Design a reversible shift register where
stages are connected in a ring, for the
following specifications
- 16R6 PAL
- Each clock pulse will cause the register to
shift left when a control input LR is 1 and to
shift right when LR is 0
- The shift register is to be loaded in parallel
from data appearing on 4 input pins under the
control of a signal LS which will cause
loading when TRUE and shifting when
FALSE
 D C B A

• DA = Q D*LR* /LS + Q B* /LR * /LS + ADAT * LS

• DB = Q A*LR* /LS + Q C* /LR * /LS + BDAT * LS
• DC = Q B*LR* /LS + Q D* /LR * /LS + CDAT * LS
• DD = Q C*LR* /LS + Q A* /LR * /LS + DDAT * LS

• LR = 1 Shift left
• LR = 0 Shift right
PAL 22V10
PAL 22V10 Macro Cell
PAL 22 V10 Configuration Modes
• Combinational Active High
• Combinational Active Low
• Sequential Active High
• Sequential Active Low
 Assignment 1
• Design the BCD to excess three code
converter using suitable PROM and give
the PROM table and connection diagram.
• Implement the following expressions using
PLA device. Indicate the conditions of the
fuses in the PLA logic diagram .

F(A,B,C,D) = ∑ m(3,4,5,6,7,10,11,15)
F(A,B,C,D) = ∑ m(1,2,5,7,15)
F(A,B,C,D) = ∏ M(3,4,5,6,7,11,12,13,14)
CPLD Structure
 CPLD Overview
• 􀁻 Higher Capacity than SPLD
􀁺 ~ 5000 gates
• 􀁻 Reasonable speed
• 􀁻 Simple Systems
Field Programmable Gate Array
• 􀁻 Two dimensional
structure
• 􀁻 Programmable
• 􀁻 Three elements:
􀁺 Logic blocks
􀁺 I/O blocks
􀁺 Interconnection wires and switches
Field Programmable Gate Array
Interconnection
Switches
Logic
Block FPGAs
• Three elements:
– Logic blocks
– I/O blocks
– Interconnection wires
and switches

I/O
Block
CAD Design Flow
DESIGN CONCEPTION

DESIGN ENTRY
(Truth Table, Schematic capture, HDL)

INITIAL SYNTHESIS TOOLS

(Simple synthesis, Translation, Merge)

FUNTIONAL SIMULATION
No Design correct?
Yes
Logic synthesis
Physical design
Timing simulation
CAD Design Flow
DESIGN CONCEPTION

DESIGN ENTRY
(Truth Table, Schematic capture, HDL)

INITIAL SYNTHESIS TOOLS

(Simple synthesis, Translation, Merge)

FUNTIONAL SIMULATION
No
Design correct?
Yes
Logic synthesis
Physical design
Timing simulation
•
Overview
Two Common Languages
of HDLs
– Verilog
– VHDL
• Other
– SystemC
• Open source, C++ code for hardware modeling
– CDL (Computer Design Language)
• Simple academic language, data flow level, developed in
1965
– ISPS (Instruction Set Processor Specification)
• Single level of abstraction, Developed in 1971
– AHPL (A Hardware Programming Language)
• Data flow & structural levels, Unfamiliar syntax, Full support
by design tools, developed in 1970
– ABEL (Data I/O Corporation, now Lattice Semiconductor)
– AHDL (Altera Corp.)
– CUPL (Logical Devices Inc.)