Computer Architecture I

Luai M. Malhis, PhD

• Course covers:
Processor design and implementation
Memory Design and implementation
Text Book: Computer Organization and Design,
The Hardware/Software Interface by Hennessy and
Patterson.

• Course grading:
Midterm Exam : 30%
Homework Assignments: 20%
Final Exam : 50%,
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 Computer Components

All general-purpose computers require the following hardware

components:
•Memory: enables a computer to store, at least temporarily, data and
programs.
•Mass storage device: allows a computer to permanently retain large
amounts of data. Common mass storage devices include disk drives
and tape drives.
•Input device : usually a keyboard and mouse, the input device is the
conduit through which data and instructions enter a computer.
•Output device : a display screen , printer , or other device that lets
you see what the computer has accomplished.
•Central processing unit (CPU): the heart of the computer, this is the
component that actually executes instructions.
 What is Computer Architecture?
The architecture of a processor is a description of its basic
components and of its basic operations.

Computer architecture is a set of rules and methods that describe

the functionality, organization, and implementation of computer
systems

When we study computer architecture we analyze its:

• Structure: static arrangement of the parts
• Organization: dynamic interaction of the parts and their control
• Implementation: design of specific components
• Performance: analytical study of the system speed.
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 Different processor architectures
• Each processor family has its own architecture.
• Assembly language is a programming view of the architecture of a
particular processor.
• Each type of processor has its own assembly language.
• When you study an assembly language, you get an abstract view of
the architecture of a particular processor.

• Designing and implanting a processor is done in two steps

 First, We must define the Instruction Set Architecture.
The ISA’s defines the functions and capabilities of the CPU.
 Second, We define and implement the micro-architecture.
We study s the processor’s internal organization that defines
datapaths components, and how instructions are executed.
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 Instruction Set Architecture (ISA)

• ISA is the interface between hardware and software

• ISA is what is visible to the programmer (and ISA might be
different for O.S. and Applications)
• ISA consists of:
– instructions (operations and how they are encoded
(opcodes))
– information units (size, how they are addressed etc.)
– registers (or more generally processor state)
– Addressing modes: literal, direct, register etc.
– input-output control: interrupts

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 Evolution of ISA’s

• ISA’s have changed over computer “generations”.

• A traditional way to look at ISA complexity encompasses:
– Number of addresses per instruction (number of operands)
– Regularity/size of instruction formats (data sizes and types)
– Instruction Length and Format
– Addressing modes ( literal, direct , indirect, relative,
displacement)

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 The Different ISA’s
Over the years many ISA’s have been proposed

• Accumulator Based:
One operand is specified in the instruction (memory address
or constant). The other operand is implicit in the accumulator.
• Stack Based: Zero operands are specified in the instruction. All
operands are implicit on top of the stack.
• Registers: All specified operands can be registers or constants.
No memory address specified in the instruction. (MIPS)
• Register –Memory: At most on operand Can be a memory address.
other operands can be register or constant.
• All Memory: operands can any combination of registers or memory
Even all three operands can be in memory (VAX)
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 Accumulator Architecture

One operand must be in the accumulator as source and destination

•A = B+C
Load B
Add C
Store A

A = B/5 + C;
Load B
Div 5
Add C
Store A
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 Stack Architecture
All operands must be on the stack
•A = B + C;
push B
push C
add
pop A

A = B/5 + C
push B
push 5
div
push C
add
pop A
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 Using Register Only (MIPS)

ALL Operands must be in Registers or at most one constant in an instruction

A= B+C
LOAD R1, B
LOAD R2, C
ADD R3,R1,R2
STORE R3,A

A =B+5
LOAD R1,B
ADD R2,R1,5
STORE R2,A

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 Register-Memory and Memory-Memory
• X86 one operand in memory
A = B+C
Mov AX, B
ADD AX,C
MOV A,AX
You Do A = B/5 - C

• VAX ALL Operands in Memory

A =B+C
ADD A,B,C
You Do A = B/5 – C;

* 11
 ISA’s classifications

• Complex instruction set computers (CISC): 60’s and 70’s

were very complex Necessary to reduce the number of
instructions required to fit a program into memory.
However, also greatly increased the complexity of the
ISA as well. The Philosophy is build a complex processor

and keep small program size.

• Reduce instruction Set Computers: The Goal is to reduce

the complexity of the ISA while maintaining or increasing
performance? The philosophy is large and we need to
optimize the processor design to improve performance
since and design simple instruction set. Program size is
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not an issue. Focus on simplify and fast execution.
 CISC Design

• Complex Instruction Set Computers were very complex

• Necessary to reduce the number of instructions required to
fit a program into memory.
• However, also greatly increased the complexity of the ISA
as well.
• How do we reduce the complexity of the ISA while
maintaining or increasing performance? Go to RISC

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 Reduced Instruction Set Computer (RISC)
• John L. Hennessy
• Dave Patterson
• MIPS, 1981
• RISC Project, 1982
• Stanford
• UC Berkeley
• Simple pipelining, keep full
• RISC-I: ½ transistors & 3x
• Influences: MIPS computer
faster
system, PlayStation, Nintendo
• Influences: Sun SPARC,
namesake of industry
 Reduced Instruction Set Computer (RISC)
• MIPS Design Principles

• Simplicity favors regularity

– 32 bit instructions

• Smaller is faster
– Small register file

• Make the common case fast

– Include support for constants

• Good design demands good compromises

 Reduced Instruction Set Computer

• MIPS = Reduced Instruction Set Computer (RlSC)

– small number of instructions are 32 bits each, 3 formats
– all operands in registers
• almost all are 32 bits each
– Few addressing mode 3 to 4 : e.g Mem[reg + imm]

• x86 = Complex Instruction Set Computer (ClSC)

– Large number of instructions, 1 to 15 bytes each
– operands in dedicated registers, general purpose registers,
memory, on stack, …
• can be 1, 2, 4, 8 bytes, signed or unsigned
– 10s of addressing modes
• e.g. Mem[segment + reg + reg*scale + offset]
 Instruction Set Design

• All the instructions executed by the CPU

• User view of the Machine (Abstraction)
• Describes machine layout and organization
• The programmer’s view of the machine (Assembly)
• Hardware dependent (Each has it own assembly)
• Two types CISC and RISC
• Design for the common case: Hardware/Softwarefaster
• Smaller is always faster: register, cache, memory, disk
• Technology and Cost plays a major Role

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 Addresses per instruction

• RISC machines
– Load-store and branches: 1 memory address + 1 or 2 registers
– All other 3 registers or 2 registers + immediate
• CISC machines
– Most of them: Two addresses
( destination ← source op.
destination)
– One operand is a register; other is either register, immediate,
or given by memory address
– Some special instructions (string manipulation) can have two
memory addresses

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 Regularity of instruction formats

• Started with fixed format (ease of programming in

“machine language”; few instructions)
• Then more flexibility (assembler/compiler): three or four
instruction formats, not necessarily the same length
• Then strive for memory compactness. Complex, powerful,
variable length instructions (x86)
• Back to regular instruction sets: few formats, instructions
of the same length (memory is cheap; instructions must be
decoded fast)

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 Number of instruction formats
• RISC: three or four (instructions have same length)
To Keep design simple and decoding fast.
• CISC
– Several formats, each of fixed (but maybe different)
lengths. Decoding Slow.
– Variable length instructions (depends on opcode,
addressing of operands etc. Intel x86 instructions from
(1 to 17 bytes) To keep program size small.
– One instruction in CISC may requires executing many
instructions in RISC.
– Therefore same high level language program compiles to
more machine instructions in RISC Compared to CISC.
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 Addressing modes

• In early machines: immediate, direct, indirect

• Then index + base (sum of 2 registers instead of -- or in
addition to -- index +displacement)
• All kinds of additional modes (indirect addressing, auto-
increment, combinations of the above etc.)
• In general RISC
– Immediate, indexed, and sometimes index + base (IBM Power PC)
• CISC
Complex addressing modes ( See VAX) machine next slide

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 A sample of VAX addressing modes

• Immediate (with even some small f-p constants)

• Direct (register) One instruction for each I-unit type
• Indirect (deferred)
• Autodecrement (and autoincrement) . The register is
incremented by the I-unit type before (after) the operand is
accessed
• Displacement (like MIPS indexed)
• Index like displacement but offset depends on the I-unit
• Combination of the above and more

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 Examples
• CLRL register (clears a whole register)
• CLRB register (clears the low byte of the register)
• CLRL (register) clears memory add whose add. is in reg.
• CLRL (register)+ as above but then register is incr. by 4
• CLRL @(register)+ as above with 1 more level of indirection
(register points to address of address)
• CLRL offset(register) Register + offset mult .by 4 for L, by 1
for B etc
• CLRL offset[register] similar but use offset + 4 * register
• CLRL 12(R4)+[R1] clear word at add. R4 + 12*4 + R1*4
then add 4 to R4
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 RISC Processor

• MIPS family outgrowth of research at Stanford (Hennessy)

First RISC Architecture
• Sun family outgrowth of research at Berkeley (Patterson)
• IBM Power/PC family outgrowth of research at IBM
• HP Precision architecture
• Currently all new processor are based on RISC.

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 RISC vs. CISC
Complex instruction set computer (CISC):
– Philosophy : Memory available is small optimize memory usage by reducing
memory needed to store program.
– Characteristics:
• Large instruction set; Complex operations; Complex addressing modes;
• Complex hardware, long execution time of a single instruction.
• Minimum number of instructions needed for a given task;

Reduced instruction set computer (RISC):

– Philosophy : Memory is large optimize instruction set and execution time.
– Characteristics:
• Small instruction set; Large number of registers;
• Simple instructions to allow for fast execution (fewer steps);
• Only read/write (load/store) instructions should access the main memory,
• Simple addressing modes to allow for fast address computation;
• Fixed-length instructions with few formats for fast instruction decoding;
• simpler and faster hardware implementation, pipelined architecture.
 ARM Processor Vs X86 architecture
RISC Architecture CISC Architecture
Used in current mobile Used in the building PC
devices based on IOS and based on mac (apple) and
Android Operating systems windows operating systems

The x86 architectures were based on the Intel 8086 microprocessor chip, initially
released in 1978. Intel Core 2 Duo – an example of an x86-compatible, 64-bit
multicore processor. AMD Athlon (early version) – a technically different but fully
compatible x86 implementation. Am386, released by AMD in 1991.The x86 architecture
Many millions of this processor architectures are produces each year for PCs
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 ARMDroid vs WinTel

• Android OS on Windows OS on Intel

ARM processor (x86) processor
 Future Architecture is RISC V

• RISC-V (pronounced "risk-five") is an open instruction set

architecture (ISA) based on established reduced instruction
set computing (RISC) principles. In contrast to most ISAs,
the RISC-V ISA can be freely used for any purpose,
permitting anyone to design, manufacture and sell RISC-
V chips and software.

• Many of the features of the RISC V architecture are

similar to the mips architecture studying mips that we will
study in details for the rest of the semester.

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Computer structure: Von Neumann model
Data +
CPU path
Control

Memory control ALU I/O

hierarch
y
PC
Registers
state

Memory
I/O bus
bus

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 Some Computer families

• Computers that have the same (or very similar) ISA

– Compatibility of software between various implementations
• IBM
– 704, 709, 70xx etc.. From 1955 till 1965
– 360, 370, 43xx, 33xx From 1965 to the present
– Power PC
• DEC
– PDP-11, VAX From 1970 till 1985
– Alpha (now Compaq, now HP) in 1990’s

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 More computer families
• Intel
– Early micros 40xx in early 70’s
– x86 (086,…,486, Pentium, Pentium Pro, Pentium 3, Pentium 4) from 1980
on
– IA-64 (Itanium) in 2001
• SUN
– Sparc, Ultra Sparc 1985 on
• MIPS-SGI
– Mips 2000, 3000, 4400, 10000 from 1985 on

Today there are many more different computer families and

architectures especially in the advent of mobile computing.
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 Another important issue in ISA definition is
Processor Memory Interface
• The CPU interacts closely with primary storage, or
main memory, referring to it for both instructions and data.
Memory holds both program instructions and data at the
time the computer is executing a program.

• RAM provides the workspace within which a CPU works.

Every location in RAM has a numbered address, and RAM
is accessed strictly by that address.

• How data is interpreted at each address depends if it is

instruction or data and also on its Endianness (little endian
or big endian).

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 Information units

• Basic unit is the bit (has value 0 or 1)

• Bits are grouped together in information units:
– Byte = 8 bits
– Word = 4 bytes
– Double word = 2 words
– etc.

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 Memory addressing
• Memory is an array of information units
– Each unit has the same size
– Each unit has its own address
– Address of an unit and contents of the unit at that address are
different
0 -123
1 17
2 0
contents
address

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Big Endian and Little Endian

To load word or store word instruction uses only one memory address.
The lowest address of the four bytes is used for the address of a block of four
contiguous bytes. (we address x we access x, x+1, x+2 and x+3)

How is a 32-bit pattern held in the four bytes of memory? There are 32 bits in
the four bytes and 32 bits in the pattern, but a choice has to be made about
which byte of memory gets what part of the pattern. There are two ways that
computers commonly do this:

Big Endian Byte Order: The most significant byte (the "big end") of the data
is placed at the byte with the lowest address. The rest of the data is placed in
order in the next three bytes in memory.

Little Endian Byte Order: The least significant byte (the "little end") of the
data is placed at the byte with the lowest address. The rest of the data is
placed in order in the next three bytes in memory.
In these definitions, the data, a 32-bit pattern, is regarded as a 32-bit unsigned
integer.* The "most significant" byte is the one for the largest 35 powers of two:
231, ..., 224. The "least significant" byte is the one for the smallest powers of two:
 Big-endian vs. little endian

• Byte order within a word:

3 2 1 0 Little-endian
(we’ll use this)

0 1 2 3 Big-endian

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For example, say that the 32-bit
pattern 0x12345678 is stored at
address 0x00400000.

The most significant byte is

0x12;

The least significant is 0x78.

Within a byte the order of the

bits is the same for all
computers (no matter how the
bytes themselves are
arranged).

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 Memory alignment
means when storing data in memory place the data at a memory address divisible
by its size without remainder.

Example:
if data size in 4 bytes (int) it must be stored at addresses: 0,4,8,12
if data size in 2 bytes (short) it must be stored at addresses: 0,2,4,6
if data size in 8 bytes (double) it must be stored at addresses: 0,8,16,24
if data size is 1 byte (char) if can be stored at any memory address.

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 Reason For memory Alignment

Improve system's performance due to the way the CPU handles

memory. Most CPUs can access only memory aligned addresses.
Each time we access group of 4 bytes.
0,1,2,3 first group
4,5,6,7 second group and
8,9,10,11 third group.

Aliment is necessary to reduce the number of times we need to go

to memory to get data.
If aligned to read a word I go to memory once 0,1,2,3
If not aligned word is stored 5,6,7,8 I will nee to go to memory
twice and getting data takes even longer for doubles. If short is
stored at 7,8 then we need to go to memory twice because once for
G1, 4,5,6,7 to get byte 7 and and another access G2 8,9,10,11 to
get bytes 8.
 Studying Computer Architecture Benefits :

Hardware point of view:

It Deals with the components and their connection in a system. Computer
Architecture helps us to understand the functionalities of a system. It tells
us how exactly all the units in the system are arranged and interconnected .
It gives us knowledge to design, develop, and implement new processors.

Software Point view:

It explores how machines are designed, built, and operate. Knowing
what's inside and how it works will help us design, develop, and
implement applications better, faster, cheaper, more efficient, and easier
to use because we know how the machine works.

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