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3 Top Level View

The document discusses the basic functions and interconnections of computer components from a top level view. It describes the instruction cycle process including fetch and execute cycles. It also covers interrupts, how they are handled through interrupt cycles, and how multiple interrupts can be handled sequentially or nested.

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7 views

3 Top Level View

The document discusses the basic functions and interconnections of computer components from a top level view. It describes the instruction cycle process including fetch and execute cycles. It also covers interrupts, how they are handled through interrupt cycles, and how multiple interrupts can be handled sequentially or nested.

Uploaded by

Manar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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William Stallings

Computer Organization
and Architecture
6th Edition

Chapter 3
Top Level view of Computer Functions and
Interconnections
Computer Components:
Top Level View
What is a program?
• A sequence of steps
• For each step, an arithmetic or logical operation is done
• For each operation, a different set of control signals is needed
Instruction Cycle
• Two steps:
• Fetch
• Execute
Fetch Cycle
• Program Counter (PC) holds address of next instruction to fetch
• Processor fetches instruction from memory location pointed to by PC
• Increment PC
• Unless told otherwise
• Instruction loaded into Instruction Register (IR)
• Processor interprets instruction and performs required actions
Execute Cycle
• Processor-memory
• data transfer between CPU and main memory
• Processor I/O
• Data transfer between CPU and I/O module
• Data processing
• Some arithmetic or logical operation on data
• Control
• Alteration of sequence of operations
• e.g. jump
• Combination of above
Interrupts
• Mechanism by which other modules (e.g. I/O) may interrupt
normal sequence of processing
• Most Common Classes of interrupts:
• Program
• e.g. overflow, division by zero
• Timer
• Generated by internal processor timer
• Used in pre-emptive multi-tasking
• I/O
• from I/O controller to signal completion of an operation or an error
• Hardware failure
• e.g. memory parity error, or power failure
Interrupt Cycle
• Added to instruction cycle
• Processor checks for interrupt
• Indicated by an interrupt signal
• If no interrupt, fetch next instruction
• If interrupt pending:
• Suspend execution of current program
• Save context
• Set PC to start address of interrupt handler routine
• Process interrupt
• Restore context and continue interrupted program
Transfer of Control via Interrupts
Instruction Cycle with Interrupts
Instruction Cycle (with Interrupts) - State
Diagram
Multiple Interrupts
• Disable interrupts
• Processor will ignore further interrupts whilst processing one interrupt
• Interrupts remain pending and are checked after first interrupt has been
processed
• Interrupts handled in sequence as they occur
• Define priorities
• Low priority interrupts can be interrupted by higher priority interrupts
• When higher priority interrupt has been processed, processor returns to
previous interrupt
Multiple Interrupts - Sequential
Multiple Interrupts – Nested
Time Sequence of Multiple Interrupts
Clock speed and instructions per second
• Quarts crystal generates high frequency signal  frequency is f
• 1GHz processor receives 1 billion pulse every second --- clock rate
• One pulse is clock cycle
• The time between pulses is the cycle time : t =1/f
• One instruction takes several cycles
Instruction execution rate
• is instruction count in one program
• cycle per instruction for instruction type I
• Different instructions require different cycles

• Overall CPI is
Program time
example
F=400 MHz

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