IAS Computer / Von Neumann

Architecture and Harvard Architecture

Introduction to the IAS Computer
• The most famous first-generation computer
• Design approach used – stored-program concept
• 2 types of computers generally exist
• Fixed-program computers – function is specific and cannot be programmed
(e.g.: calculator)
• Stored-program computers – can be programmed to carry out different tasks
and applications can be stored on them
• Prototype of all general-purpose computers
• Designed by Jon von Neumann and his colleagues at the Princeton Institute for
Advanced Studies
• Also referred to as the Von Neumann architecture and is characterized by a shared
memory for programs/instructions and data
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 IAS Computer
Structure
• Components:
• Main memory which
stores both data and
instructions
• Single bus for
memory access
• Arithmetic and logic
unit
• Control unit which
interprets instructions
and causes them to be
executed
• Input-output (I/O)
equipment
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Memory
• The memory of the IAS consists of 4,096 storage locations, called words, of
40 binary digits (bits) each.
• Both data and instructions are stored there.
• Numbers are represented in binary form, and each instruction is a binary code.
• Each number is represented by a sign bit and a 39-bit value.
• A word may alternatively contain two 20-bit instructions consisting of
• an 8-bit operation code (opcode) specifying the operation to be performed
• a 12-bit address designating one of the words in memory (numbered from 0 to
999)

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Format of Data and Instruction

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Control Unit and ALU Registers
• Memory buffer register (MBR): Contains a word to be stored in memory or sent to
the I/O unit, or is used to receive a word from memory or from the I/O unit.
• Memory address register (MAR): Specifies the address in memory of the word to
be written from or read into the MBR.
• Instruction register (IR): Contains the 8-bit opcode instruction being executed.
• Instruction buffer register (IBR): Employed to hold temporarily the right-hand
instruction from a word in memory.
• Program counter (PC): Contains the address of the next instruction pair to be
fetched from memory.
• Accumulator (AC) and multiplier quotient (MQ): Employed to hold temporarily
operands and results of ALU operations.
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IAS Computer Instructions
• The IAS computer had a total of 21 instructions, which can be grouped as
• Data transfer: Move data between memory and ALU registers or between two
ALU registers.
• Unconditional branch: Normally, the control unit executes instructions in
sequence from memory. This sequence can be changed by a branch
instruction, which facilitates repetitive operations.
• Conditional branch: The branch can be made dependent on a condition, thus
allowing decision points.
• Arithmetic: Operations performed by the ALU.
• Address modify: Permits addresses to be computed in the ALU and then
inserted into instructions stored in memory. This allows a program
considerable addressing flexibility.
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IAS Computer
Instruction Set

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IAS Instruction Cycle
• The IAS operates by repetitively
performing an instruction cycle.
• Each instruction cycle consists of
two sub-cycles
• Fetch
• Execute

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Von Neumann Bottleneck
• Two factors affecting the CPU performance in a Von Neumann computer:
• Instructions can only be done one at a time.
• Instructions can only be carried out sequentially.
• These factors result in what is commonly referred to as the ‘Von Neumann
bottleneck’.
• A Von Neumann processor may be provided with more cache, more RAM, or
faster components, but for a significant gain in performance, there needs to be a
bigger change.
• This architecture is very important and is used in our PCs and even in Super
Computers.

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Harvard Architecture
Address
• The Harvard architecture has bus
two separate memory spaces Program
dedicated to program code Memory ALU
and to data, respectively, and Data bus
two corresponding address I/O
and data buses for accessing CPU Devices
the two memory spaces. Address
bus
• The Harvard processor offers Data Control
fetching & executions in Memory Unit
parallel. Data bus

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Features of Harvard Architecture
• There is a separate memory for data and program.
• A separate data path and instruction path is available.
• Fetching of data and instructions can be done simultaneously.
• Different sized cells can be allowed in both the memories to make effective use of
resources.

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Von Neumann vs Harvard Architecture
Von Neumann Architecture Harvard Architecture
Memory is common for both instruction Separate memory for instruction and data
and data
Common bus between memory and CPU Separate buses for instruction and data
for both instruction and data memories
Two clock cycles required for the Only one clock cycle is required for the
execution of an instruction execution of an instruction
Data transfer and instruction fetches Data transfer and instruction fetches can
cannot be done simultaneously be done simultaneously
Control unit design is simple Control unit design is complex and hence
the development cost is higher

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RISC and CISC
RISC (Reduced Instruction Set Computer)
• To execute each instruction, if there is separate electronic circuitry in the control
unit, which produces all the necessary signals, this approach of the design of the
control section of the processor is called RISC design. It is also called hard-wired
approach.
• Examples of RISC processors: IBM RS6000, MC88100; DEC’s Alpha 21064,
21164 and 21264 processors
• It is a highly customized set of instructions used in portable devices due to system
reliability such as Apple iPod, mobiles/smartphones, Nintendo DS

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RISC Features
Hardwired
• Has small and limited number of instructions control Data Path
• Uses hardwired control unit unit
• Consumes less power and are having high
performance
Instruction Data
• Each instruction is very simple and consistent. Cache Cache
• Uses simple addressing modes.
• RISC instruction is of uniform fixed length.
(Instruction) (Data)
Main Memory

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CISC (Complex Instruction Set Computer)
• If the control unit contains a number of microelectronic circuitry to generate a set
of control signals and each micro-circuitry is activated by a microcode, this design
approach is called CISC design.
• Examples of CISC processors: Intel 386, 486, Pentium, Pentium Pro, Pentium II,
Pentium III ; Motorola’s 68000, 68020, 68040, etc.
• It has a large collection of complex instructions that range from simple to very
complex and specialized in the assembly language level, which takes a long time
to execute the instructions.

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CISC Features
Instruction
• CISC chips have a large amount of different Control
& Data
and complex instructions. unit
Path
• CISC machines generally make use of
complex addressing modes.
Microprogram
• Different machine programs can be executed Control Cache
on CISC machine. Memory
• CISC machines uses micro-program control
unit.
• CISC processors are having limited number Main Memory
of registers.

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RISC vs CISC
CISC RISC
Emphasis on software Emphasis on hardware
Multiple instruction sizes and Instructions of the same set with a
formats few formats
Less registers used More registers used
More addressing modes Fewer addressing modes
Extensive use of Complexity in compiler
microprogramming
Instructions take varying amount of Instructions take one cycle time
cycle time
Pipelining is difficult Pipelining is easy

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