VLSI Design Verification and

Testing

Combinational and Sequential ATPG

EEE600 Winter 2012-13

 Summary of last courses
In the previous lectures we have seen:
• the necessity to test VLSI systems, and related costs/benefit
analysis
• how faults are modeled
• how faults are simulated
• how the quality of testing is measured

Let us now focus on how test vector patterns are generated

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 Course outline

• Structural vs. functional test
• Scan design First, we have to study
• Search space abstractions
 a number of useful
concepts
•
•
Five values algebra
Path sensitization 

• Combinational ATPG algorithms
– D-algorithm


In a second phase, we
– other algorithms will study actual
algorithms


• Sequential algorithms

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 Functional test
Computational burden of functionally testing a 64-bit adder

A B Carry-in
64 64 1

+
64 1

Sum Carry-out

• the adder has 129 inputs and 65 outputs

• in order to completely exercise its functionality, we need 2129 input patterns,

generating 265 output patterns

• using a 1GHz ATE, this takes 2.15x 1022 years, roughly

EEE600 Winter 2012-13

 Structural test (1)
Structural representation of a 1-bit full-adder

A
B
Sum generation of sum
Carry-in

Carry-out generation of
carry

16 stuck-at fault locations

… to be repeated 64x for a 64-bit adder

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 Structural test (2)
Computational burden of structurally testing a 64-bit adder (approximate !)

• the total structural fault list has 64 x 16 = 1024 faults

• thus, 1024 vectors are needed for a full structural test

• using a 1GHz ATE, this takes 1.024 x 10-7 s

The functional and structural examples achieve the exact same fault coverage

In practice:
• a subset covering <75% faults is provided by the designer as functional
test-patterns
• ATPG is applied to supplement and raise the coverage to >98% stuck-at
fault coverage

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 ATPG
Automatic Test-Pattern Generator (ATPG) algorithm:

• inject a fault into a circuit

• activate the fault, and cause its effects to propagate to a circuit primary
output

• if the circuit output is different from what would be expected from a fault-
free circuit, then the fault can be detected

But also:

• detect redundant or unnecessary circuit logic

• prove whether one circuit implementation matched another circuit

implementation

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 Search space abstractions
A logic circuit is represented as binary tree representation of the AND gate
direct acyclic graph with a root and cj
vertex v
One only path leads from a vertex to x2
the root
0 1
Only two decisions are possible from
a node x1 x1
0 1 0 1
This is a binary decision tree
0 0 0 1

“backtracking”
The tree represents all possibilities for input patterns x1 and x2
The leaf nodes represent the good machine output for the selected inputs

All ATPG algorithms search a similar tree to find test-patterns

• each node of the tree represents a decision variable
• when a conflict or no solution is found, the algorithm dictates reversing
previous decision: backtrack
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 Search space abstractions (2)
The Binary decision diagram (BDD) is
obtained by reducing the decision tree
It represents the optimal form of a switching cj
function
x2

1
Any switching function can be described 0
x1
by a BDD
0 1

0 1
In order to read the diagram:
• start from root node (top) binary decision diagram
• the product of all visited nodes forms representation of the circuit
the maxterms/minterms
• the output value is read at the leaf

e.g. rightmost path: x1 · x2 = 1

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 ATPG
The automatic test pattern generation makes use of these search space
abstractions

An internal representation of explored, infeasible, tree is being kept in

memory

cj
x2
Searched and Infeasible
0 1 Unexplored

x1 x1
0 1 0 1

0 0 0 1

Present Assignment

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 Roth’s 5-valued algebra
In order to proceed ATPG in one single pass of the algorithm, a high-order
algebra representing both the good and failing machine simultaneously is
presented

D 1 in true circuit, 0 in faulty circuit 1 1 in both true and faulty circuit

D 0 in true circuit, 1 in faulty circuit 0 0 in both true and faulty circuit

X unknown value in either true or

faulty circuit
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 Forward implication
A forward implication results when the inputs to a logic gate are sufficiently
labeled so that the output can be uniquely determined

D three examples
D
1
AND gate forward implication
table

D D
0

D D
0

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 Backward implication
The backward implication is the unique determination of all gate inputs
when the gate output and some of the inputs are given

three examples
1 1
1
Used by the ATPG in the
justification step, as
D D backtracing procedure, where
given an output objective, the
0 input conditions are traced in a
backward pass

D D
backtracking  backtracing
0

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 Fault cone and D-frontier
1 1
0 Fault Cone

s-a-1 1
D D x D-Frontier

x
0 0

Fault cone set of hardware that can be reached while performing a forward
tracing, starting at the fault site
D-frontier set of gates closest to POs with D or D at the input and X at the
output

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 Path sensitization method
Preferred ATPG method, consisting of three steps

1. fault sensitization a fault is activated by forcing the signal driving it to the

opposite value from the fault

1. fault propagation the fault effect is propagated to a PO (primary output)

1. line justification internal signal assignments previously made to sensitize

or propagate are justified by setting PIs (primary inputs) of the circuit

A conflict may arise when an assignment contradicts with a previously made

assignment

Backtrack is then needed, where a previously made assignment is discarded,

and an alternate assignment selected

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Circuit example for path sensitization (1)

1 f
s-a-0
D z
a
c
g b

Path sensitization of this circuit will demonstrate conflict, and backtrack.

Step1: assuming the second input s-a-0, fault activation requires that this
node be controlled to logic 1, thus causing a D downstream of the fault

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Circuit example for path sensitization (2)
0
1 f
s-a-0 0 0
D D
z
a D D
c
g b
1

Step2: fault propagation, decision path scenario is a-b-c-z

– all off-path values must be non-controlling, i.e. g=1, f=0
– indeed, D-bar shows up at the output
Step3: justification
– backtracing f=0 requires that both inputs of the OR gate be at logic 0
– this creates a conflict since the nodes downstream of the fault should be at D
– backtracking is needed

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Circuit example for path sensitization (3)
0 D
1 f
s-a-0 D
D 1
z
a D D
c
g b
1

Step2: backtracking, we try simultaneous propagation through paths a-b-c-z

and f-z
– this solution must be abandoned as the fault does not propagate to a PO
– the D-frontier is said to disappear

– backtrack, again …

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Circuit example for path sensitization (4)
0 D
1 f
s-a-0 D
D
1 z
a 0
0 c
g b

Step2: backtracking, we try path f-z

– D propagates through the first OR if the other input is set to logic 0
– c=0, which allows successful propagation of D to z
Step3: justifying
– a=1 causes c=0
– this creates a conflict again,
– backtracking is needed, again

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Circuit example for path sensitization (5)
0 0 D
1 f
s-a-0 D
D
z
a 0
c
g b
0 0
x

Step3: justifying
– g=0 causes c=0
– no conflict remains, the vector is discovered as 010x

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 Circuit example for path sensitization (6)
A=0
B=1 f
s-a-0
Z=D
z
a
c
g b
C=0
E=x

So, what have we achieved so far … ?

remember that we do not have access to probe or control any of the

internal nodes while doing the test measurement

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Circuit example for path sensitization (7)
In conclusion

The test for the s-a-0 fault is vector ABCD=010x, and produces output

• Z=1 in the good machine, and

• Z=0 in the failing machine

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 So, what do we do now ?
The path sensitization method works fine …

… however, a number of extra steps must be taken in order to

to have an algorithm that can be processed by a machine

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 D-algorithm (D-ALG)
First complete ATPG algorithm, first developed in 1966
D-ALG is the root of a number of improved algorithms

Following steps are presented in next slides

• process definitions
– singular cover
– D-cube
– D-intersection operation

• implication procedure
– D-drive

• general method, and examples

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 Singular cover
Minimal set of logic signal assignments to show essential prime implicants of
Karnaugh map

– it is presented in the form of a reduced truth table, still covering all cases using
(1, 0, X) - for clarity purposes, writing the X is often omitted in large tables

example 1: singular cover of a two-input AND gate

A
d
B

example 2: singular cover of AND and NOR in depicted circuit

A d
G1

G3 F

B e
G2
C

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 Essential prime implicant (1)
A Karnaugh map is a two-dimensional graphical representation of a complex
Boolean operator input-output function, with a practical limitation of input
variables in a range of two to six.

Each axis holds one or more variables, which are to be localized in pairs or
triplets, and numbered following a Gray code. The Gray code dictates that only
one binary value may change between two adjacent codes.

AB A

CD 00 01 11 10
Following figure shows an example 00 0 0 1 1
of a Karnaugh table, implementing
01 0 1 1 0
the Boolean function D
11 1 1 0 0
C
10 0 1 1 1

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 Essential prime implicant (2)
Following items are recognized on a Karnaugh map

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 Essential prime implicant (3)
In the context of deriving the table of singular covers, we have to consider essential
prime implicants for the cases where the ouput is a logic 0 and a logic 1.
Applied to the specific case of two-input Boolean gates, essential prime implicants
read as follows

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Essential prime implicant (4)

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 Primitive D-cube of failure (PDF)
• collapsed truth table entry to characterize logic

– Roth’s five-valued algebra is used

– Models circuit faults:
• Stuck-at-0
• Stuck-at-1
• Bridging fault (short circuit)
• Arbitrary change in logic function

– the primitive D-cube of a failure evidences the effect of a fault on the gate output

primitive D-cube for an AND primitive D-cube for an AND

gate with Z s-a-0 gate with Z s-a-1

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 Propagated D-cube
• cubes are created by combining rows in the singular cover, exchanging inputs,
ANDind newly obtained rows, replacing D with D

• all obtained cubes constitute the set of propagated D-cubes describing the way
of propagation of fault effect through a gate

– specifies values to be applied to inputs so that a change applied to that input

causes a change of the output

Propagated D-cubes for AND

Every line represents a D-cube

D can be replaced by D

EEE600 Winter 2012-13

 D-calculus (1)
D-intersection defines how different D-cubes coexist for different gates in the
circuit

This set of rules is applied in the propagation phase, where D must be

propagated to a primary output, and justification phase

empty undefined,  or  requires inversion of D and D

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 D-calculus (2)
empty undefined:
• the cubes are incompatible
• meeting a  and during the progression of the algorithm means that the
proposed solution is not viable  backtrack to another solution

example: intersection of cubes 0XX and 1XX

0XX  1XX =  XX
these two cubes cannot coexist

 or  requires inversion of D and D:

• if both  and  occur during D-intersection, then the cubes are
incompatible
• if only  occurs, then D  D = D and D  D = D
• if only  occurs
1. transform the second cube as follows: D  D and D  D
2. then, apply D-intersect again, considering the  rule described above

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 Implication procedure

Model fault with appropriate primitive D-cube of failure (PDF)


Select propagation D-cubes to propagate fault effect to a circuit output
(D-drive procedure)


Select singular cover cubes to justify internal circuit signals (Consistency
procedure)

Regrettably, cubes are selected very arbitrarily by D-algorithm

EEE600 Winter 2012-13

 D-algorithm, top level
Number all circuit lines in increasing level order from PIs to POs;


Select a primitive D-cube of the fault to be the test cube;



Put logic outputs with inputs labeled as D (D) onto the D-frontier;


D-drive ();


Consistency ();


Return ();


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 Example 1 (1)
Generation of test vectors: circuit and truth table

d
A
G1

G3 F

B e
G2
C

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 Example 1 (2)
Preparation work: devise singular cover and propagation D-cubes tables

D-drive propagation table

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 Example 1 (3)
Step 1: fault is now considered
select a primitive D-cube for the considered fault

Fault is d s-a-0

d
A
G1 s-a-0

G3 F
In this specific case:
B e
G2 Select in the D-cube propagation table
C one cube which has a fault D at d,
where d is an output

Note that the error propagates forward from d, thus we don’t see any D in the inputs,
however A=1 and B=1 is the only combination which may propagate as a D at the output
of an AND Boolean gate

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 Example 1 (4)
Step 2: propagate the error through to a primary output (D-drive)

In this specific case:

Select one cube in the D-cube propagation table, which has a
fault D at d, where d is an input; cube c7, for example
Next, check whether the fault has propagated to the ouput; this
is the case
Finally, apply the intersection rule to both cubes that have been
selected so far

G3 is an obvious path which allows d s-a-0 to propagate to F

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 Example 1 (5.1)
Step 3: justify (consistency check)

In this specific case:

0 at node e must be justified (red square); we must find the singular cover for gate G2
In the singular cover table, find a singular cover where node e is an output and has a value equal to
0; in our case, there is only one possibility

EEE600 Winter 2012-13

 Example 1 (5.2)
Step 3: justify (consistency check)

In this specific case:

0 at node e must be justified (red square)
In the singular cover table, find a singular cover where node e is an output and has a value equal to
0; in our case, there is only one possibility
check whether there is any inconsistency at inputs of G2; all three red arrows show consistency

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 Example 1 (6)
Interpretation of the resulting final D-cube

vector 111 is a valid test for d s-a-0

if error not present, F reads 0

if error is present, F reads 1

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 Example 2 (1)
Step 1: primitive D-cube of failure E s-a-0

h m
B
Z
g
k
C
f
E
s-a-0 D

This is Roth’s original example:

J. P. Roth, “Diagnosis of Automata Failures: A Calculus and a Method,” IBM Journal, July 1966

EEE600 Winter 2012-13

 Example 2 (2)
Step 2: propagation D-cubes for Z

1
h m
B
Z
g
0 k D
C
f D
E
s-a-0 D

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 Example 2 (3)
Step 3: backward implications

1
A

1 0 1
h m
B
Z
g
0 k D
C
f D
E
s-a-0 D

Backtracing trough path m-g-h is a bad decision; in this case, a conflict

occurs on node g Backtracking is needed

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 Example 2 (4)
Step 3+: backtracking  test found

0
A

0 1 1
0 h m
B
Z
g
0 0 0 k D
C
f D
E
s-a-0 D

The test vector is: ABCE = 0001 for E s-a-0

• if the circuit is faulty (E s-a-0 active) then Z=1
• if the circuit is not faulty, then Z=0

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 Example 2 (5)
Remember that the software can not interpret the schematic of the netlist
as humans do; it only information comes from the circuit netlist, and its
internal representation as a binary tree, that the software is constructing

Here, we show the procedure as a set of tables, which is reminiscent of

the software operation

Thus from now on, we only work with tables, as if we had no prior
knowledge of the schematic

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 Example 2 (6)

Propagation D-cubes
and singular cover

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 Example 2 (7)
The primitive D-cube of failure (PDF) is cube c14
D-drive is performed, which is followed by justification
The obtained vectors are consistent
test vector(s): ABCE = X001

In the example shown here, no backtracking has been needed at any

time; this is a lucky situation

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 Discussion
The D-algorithm would fail in some cases, due to the intrinsic algorithmic
structure and to the lack of directing the algorithm, e.g. error correction
circuits.

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 PODEM
The PODEM (Path-Oriented Decision Making) algorithm introduces
several standard ATPG concepts:

• the PODEM decision tree is expanded around PI (primary input)

variables only - not around all circuit signals
– smaller and predictable search tree size in comparison with D-algorithm

• PODEM algorithm checks the existence of the D-frontier

– backtrack when D-frontier vanishes
– whereas D-algorithm would proceed with intersecting D-cubes

• PODEM introduces the concept of objectives; PIs are selected

(backtraced) to justify these objectives

• controllability measures are used to guide PODEM

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 PODEM algorithm
Start

Assign a binary value to an

unassigned primary input

Determine implications of all

primary inputs

Test yes
generated Exit - Fault tested
?

no

Test
maybe possible with
additional assigned
primary inputs
?

no

Is there no
an untried combination
Exit - Fault untestable
of values on assigned
primary inputs
?
yes
Set untried combination of
values on assigned primary
inputs

Source: P. Goel, An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits, IEEE T. Computers, Vol. C30, pp. 215-222, 1981

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 FAN
Improve PODEM by introducing novel concepts to limit ATPG search
space and speed up backtracing

• some circuit values are uniquely determined, PODEM may fail to

recognize them; FAN immediately assigns them

Many other advanced ATPG algorithm variations have been

developed. Numerous software packages are available to handle
ATPG.

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 Sequential ATPG
• A sequential circuit has memory in addition to combinational
logic.

• Test for a fault in a sequential circuit is a sequence of vectors,

which
• Initializes the circuit to a known state
• Activates the fault, and
• Propagates the fault effect to a primary output

• Methods of sequential circuit ATPG

• Time-frame expansion methods
• Simulation-based methods

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Muth’s nine-valued logic

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 Time-frame expansion
• A sequential circuit has memory in addition to combinational
logic.

• Test for a fault in a sequential circuit is a sequence of vectors,

which
• Initializes the circuit to a known state
• Activates the fault, and
• Propagates the fault effect to a primary output

• Methods of sequential circuit ATPG

• Time-frame expansion methods
• Simulation-based methods

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 Implementation (1)
PIs POs
Combinatory block

Pseudo Pseudo
PIs POs
Memory block

CLOCK

This sequential circuit can be “unrolled” into a larger

combinational circuit; this process is called time-frame
expansion …

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 Implementation (2)
Fault-detection
timeframe
v- k v- 1 v0

s- k+1 s- 1 s0 s0
s- k C M M C M C

Pseudo
memory

timeframe -k timeframe -1 timeframe 0

vk input, binary
sk state vector, nine-valued logic

Temporal copies of the combinational part are linked with pseudo-

combinational memory elements
Each temporal copy belongs to a unique timeframe

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 Implementation (3)
v- k v- 1 v0

s- k+1 s- 1 s0 s0
s- k C M M C M C

Pseudo
memory

timeframe -k timeframe -1 timeframe 0

1. use ATPG algorithms (PODEM/FAN) to determine the test

vector of the timeframe 0 (the final one)

1. use ATPG justification part to justify across timeframe -1

1. apply 2 until reaching timeframe -k, where a given initial

state is reached
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 Additional readings and references
• J. P. Roth, “Diagnosis of Automata Failures: A Calculus and a Method,”
IBM Journal, pp. 278-291, July 1966
• T. Kirkland, M. R. Mercier, “Algorithms for Automatic Test Pattern
Generation,” IEEE Design and Test of Computers, pp. 43-55, June 1988
• R.H. Klenke, R.D. Williams, J.H. Aylor, “Parallel-processing techniques for
automatic test pattern generation,” Computer, Vol. 25, No. 1, pp. 71-84,
1992
• SP. Goel, “An Implicit Enumeration Algorithm to Generate Tests for
Combinational Logic Circuits,” IEEE T. Computers, Vol. C30, pp. 215-222,
1981

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 References
• M. L. Bushnel and W. D. Agrawal, “Essential of Electronic Testing for
Digital, Memory, and Mixed Signal VLSI Circuits,” Springer, 2005
• L.-T. Wang, C.-W. Wu, X. Wen, Edts., “VLSI Test Principles and
Architecture,” Morgan Kaufmann, 2006

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