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Lec4 Slides Testbenches

The document discusses testbenches in Verilog. It explains that a testbench is used to apply test inputs to a design and observe outputs during simulation. It describes how initial and always blocks can be used to generate stimulus, and how the design under test is instantiated within the testbench. Examples of writing testbenches for basic gates and adders are provided.

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50 views30 pages

Lec4 Slides Testbenches

The document discusses testbenches in Verilog. It explains that a testbench is used to apply test inputs to a design and observe outputs during simulation. It describes how initial and always blocks can be used to generate stimulus, and how the design under test is instantiated within the testbench. Examples of writing testbenches for basic gates and adders are provided.

Uploaded by

Abdalrhman juber
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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ENCS3310

Advanced Digital Design

Lecture 4:
Testbenches
Introduction

 Testbenches
 Verilog description of environment
 Apply test inputs
 Look at outputs
Testbenches

 Would like to describe test inputs in Verilog


 Powerful
 Portable
Writing a Test Bench

 A test bench is an HDL program used for applying


stimulus to an HDL design in order to test it and
observe its response during simulation.
 In addition to the always statement, test benches use
the initial statement to provide a stimulus to the
circuit under test.
 The always statement executes repeatedly in a loop.
The initial statement executes only once starting from
simulation time=0 and may continue with any
operations that are delayed by a given number of units
as specified by the symbol #.
Writing a Test Bench (2)
initial begin
A=0; B=0;
#10 A=1;
#20 A=0; B=1;
end
 The block is enclosed between begin and
end. At time=0, A and B are set to 0. 10
time units later, A is changed to 1. 20 time
units later (at t=30) a is changed to 0 and B
to 1.
Writing a Test Bench (2)

 Inputs to a 3-bit truth table can be generated


with the initial block
initial begin
D = 3’b000; repeat
(7)
#10 D = D + 3’b001;
end
 The 3-bit vector D is initialized to 000 at time=0.
The keyword repeat specifies looping
statement: one is added to D seven times, once
every 10 time units.
Writing a Test-Bench (3)
 A stimulus module is an HDL program that has the following
form.
module testname
Declare local reg and wire identifiers
Instantiate the design module under test.
Generate stimulus using initial and always statements
Display the output response.
endmodule
 A test module typically has no inputs or outputs.
 The signals that are applied as inputs to the design module for
simulation are declared in the stimulus module as local reg
data type.
 The outputs of the design module that are displayed for testing
are declared in the stimulus model as local wire data type.
 The module under test is then instantiated using the local
identifiers.
Writing a Test-Bench (4)

The stimulus model generates inputs for the design module


by declaring identifiers TA and TB as reg data type, and
checks the output of the design unit with the wire
identifier TC. The local identifiers are then used to
instantiate the design module under test.
A simulation example from the lab
module nandgate(a,b,c);
input a,b;
output c;

nand g1(c,b,a);

endmodule
A simulation example from the lab

 Used stimulators in ActiveHDL


Not portable to other Verilog products
 Not very powerful

 We’d like to describe test inputs in Verilog


A simulation example from the lab

 We need to know Verilog way to:


 represent behaviour of a and b
 Low then high then low again

 apply these inputs to the gate


Multiple assignment to signals
initial
begin
in1= 0; in2=0;
#10ns in1=1;
#10ns in2=1;
#30ns in1=0; in2=1;
end
Normal Verilog assignment runs when RHS signal changes
There are no signals on RHS, only literal values
Statements run exactly once at beginning of simulation
This type of assignment is exempt from inertial behaviour
Multiple transitions can co-exist on queue
A test bench for the NAND gate
Test bench

in1
a G1
in2 c out1
b

 Test bench represents “world around the


device we’re simulating”
 Contains Verilog simulation of
 input generator (signal generator)
 output observer (logic analyzer)
A test bench for the NAND gate
Test bench

in1
a G1
in2 c out1
b

 It’s a closed system with no inputs or outputs:


module nand_test;

endmodule
A test bench for the NAND gate
Test bench

in1
a G1
in2 c out1
b

 It contains internal signals:


 in1, in2 that model a signal generator unit
 out1 that models the logic analyzer unit

reg in1,in2;
wire out1;
A test bench for the NAND gate
Test bench

in1
a G1
in2 c out1
b

 It contains one copy of the device we want to test


 in1, in2 are connected to its inputs
 out1 is connected to its outputs

nandgate n1(.a(in1),.b(in2),.c(out1));
A test bench for the NAND gate
Test bench

in1
a G1
in2 c out1
b

 We need to say how in1 and in2 change with time

initial
begin
in1= 0; in2=0;
#10 in1=1;
#30 in1=0; in2=1;
end
A test bench for the NAND gate
module nand_test;
reg in1,in2;
wire out1;

nandgate n1(.a(in1),.b(in2),.c(out1));

initial
begin
in1= 0; in2=0;
#10ns in1=1;
#10ns in2=1;
#30ns in1=0; in2=1;
end
endmodule

Test bench

in1
a G1
in2 c out1
b
A test bench for the fulladder
module fa_tb();
reg cin,x,y ;
wire s,cout;

fulladd fa0(cin,x,y,s,cout);

initial
begin
{cin,x,y} = 3'b000;
repeat(7)
#10ns {cin,x,y} = {cin,x,y} + 3'b001;
end

endmodule
A Test Bench for our 4-bit Adder
module adder4_tb; Open libraries

endmodule Declare port map

Testbench Work library

cin
x sum
+
y
cout
A Test Bench for our 4-bit Adder
Declare signals used in
our test bench
reg carry_in;
reg [3:0] in1,in2;
wire carry_out;
wire [3:0] sum1;

Testbench Work library


carry_in
cin
x sum
+
in1 y
in2 sum1 cout

carry_out
A Test Bench for our 4-bit Adder
Instantiate the adder
from the library
adder4 u1

Testbench Work library


carry_in
cin
x sum
cin +
in1 x sum y
in2 + sum1 cout
y
cout

carry_out
A Test Bench for our 4-bit Adder
Wire up the inputs & outputs

adder4
u1(.carryin(carry_in), .X(in1), .Y(in2), .S(sum1)
, .carryout(carry_out));

Testbench Work library


carry_in
cin
x sum
cin +
in1 x sum y
in2 + sum1 cout
y
cout

carry_out
A Test Bench for our 4-bit Adder
initial Give some values to inputs
begin and outputs
in1= 0; in2=0; carry_in=0;
#10ns in1=3;
#10ns in2=4;
#20ns in1=5;
#40ns in2=1;

end
Testbench Work library
carry_in
cin
x sum
cin +
in1 x sum y
in2 + sum1 cout
y
cout

carry_out
Verilog System Tasks
 The response to the stimulus generated by the initial and
always blocks will appear at the output of the simulator as
timing diagrams.
 It is also possible to display numerical outputs using Verilog
system tasks.
 $display – display one-time value of variables or strings
with end-of-line return,
 $write – same $display but without going to next line.
 $monitor – display variables whenever a value changes
during simulation run.
 $time – displays simulation time
 $finish – terminates the simulation

 The syntax for $display,$write and $monitor is of the form


Task-name (format-specification, argument list);
E.g. $display(%d %b %b, C,A,B);
$display(“time = %0d A = %b B=%b”,$time,A,B);
MUX2x1 Description

//Dataflow description of 2-to-1-line multiplexer


module mux2x1_df (A,B,select,OUT);
input A,B,select;
output OUT;
assign OUT = select ? A : B;
endmodule
MUX2x1 Testbench
//Stimulus for mux2x1_df
module testmux;
reg TA,TB,TS; //inputs for mux
wire Y; //output from mux
mux2x1_df mx (TA,TB,TS,Y); // instantiate mux
initial begin
$display ("Select A B Out");
$monitor("Time %0d select=%b A=%b B=%b OUT=%b",
$time,TS,TA,TB,Y);
TS = 1; TA = 0; TB = 1;
#10 TA = 1; TB = 0;
#10 TS = 0;
#10 TA = 0; TB = 1;
end
endmodule
MUX2x1 Testbench
module testmux2;

reg TA,TB,TS; //inputs for mux


wire Y; //output from mux

mux2x1_df mx (TA,TB,TS,Y); // instantiate mux


initial begin
$display (" Select A B Out");
$monitor("Time %0d select=%b A=%b B=%b OUT=%b",
$time,TS,TA,TB,Y);

{TS,TA,TB} = 3'b000;
repeat(7)
#10 {TS,TA,TB} = {TS,TA,TB} + 3'b001;
end
endmodule
MUX2x1 Testbench
initial begin
$display (" Select A B Out");
$monitor("Time %0d select=%b A=%b B=%b OUT=%b",
$time,TS,TA,TB,Y);
TS= 0; TA = 0; TB = 0;

end

always #40ns TS = ~TS;

always #20ns TA = ~TA;

always #10ns TB = ~TB;


Summary
 Test benches
 System Tasks

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