An Overview of Serial ATA Technology

Chris Erickson
Graduate Student Department of Electrical and Computer Engineering Auburn University, Auburn, AL 36849 [Link]@[Link]

Objectives
Why SATA was invented The differences between PATA and SATA How the hardware is structured to transmit and receive SATA Protocol of SATA transmission

What is PATA?
All of the below synonyms refer to a modern day PATA drive
PATA Parallel Advanced Technology Attachment

UDMA Ultra Direct Memory Access

IDE Integrated Device Electronics EIDE Enhanced IDE

More on PATA
40 & 80 wire cable option
40 wire limited to UDMA 33 MB/s and below 80 wire allowed for UDMA 66, 100, 133 MB/s

Required by ATA spec to be 5v tolerant (3.3v has been the norm for several years) Must support Master/Slave/Cable Select

SATA Basics
New Connector
Saves space More reliable More air flow

Connector has 4 transmission wires

Tx differential pair Rx differential pair

SATA Basics
SATA I for 1.5Gbps ~ 150MB/s SATA II for 3.0Gbps ~ 300MB/s Provides support for legacy command set

Includes new commands for SATA BIST and power management

Connectivity
Serial ATA is point-to-point topology
Hosts can support multiple devices but requires multiple links 100% available link bandwidth

Failure of one device or link does not affect other links

Link Characteristics
SATA uses full-duplex links
Protocol only permits frame transfer in one direction at a time Each link consists of a transmit and a receive pair

SATA uses low voltage levels

Nominal voltage +/-250mV differential

Power Management
SATA has
Phy Ready Capable of sending and receiving data. Main phase locked loop are on and active Partial Physical layer is powered but in a reduced state. Must be able to return to Phy Ready within 10 us. Slumber Physical layer is powered but in a reduced state. Must be able to return to Phy Ready within 10 ms.

ATA also defines IDLE, STANDBY, and SLEEP

Necessary for newer laptop & mobile devices

SATA Architectural Model

Host Control Software
Buffer Memory DMA management
Application

Device Control Software Buffer Memory DMA management

Serial digital transport control

Transport

Serial digital transport control

Link

Serial digital link control

Serial digital link control

Serial physical interface

Physical

Serial physical interface

Host Layers

Device Layers

Physical Layer
Transmission (Tx) and Reception (Rx) of a 1.5Gb/s serial stream Perform power on sequencing Perform speed negotiation Provide status to link layer Support power management requests Out-of-Band (OOB) signal generation and detection

Out of Band
Part of normal power on sequence Allows host to issue a device hard reset Allows device to request a hard reset Brings device out of low power state

Out of Band Signals

COMRESET
Always originated by the host Forces a hard reset in the device Used to start link initialization

COMINIT
Always originated by the device Requests a link reset Issued by device in response to COMRESET

Out of Band Signals (cont.)

COMWAKE
Can be originated by either host or device Used as final phase of OOB initialization Used to bring out of low power & test states
Exit Partial Exit Slumber Exit BIST

Out of Band Signal Forms

COMRESET / COMINIT

320 ns 106.7 ns

COMWAKE

106.7 ns

106.7 ns

Out of Band Signaling Protocol

Host

Device

SATA Port Model

Tx +

Data In
Align Generator

Serializer Tx Clock

Tx -

Phy Reset Phy Ready Slumber Partial

Analog Front End

Port Control Logic

SPD Select SPD Mode System Clock

Rx +

Data Out
RX Clock COMRESET / COMINIT

Deserializer

Clock & Data Recovery OOB Detect

Rx -

COMWAKE

SATA Architectural Model

Host Control Software
Buffer Memory DMA management
Application

Device Control Software Buffer Memory DMA management

Serial digital transport control

Transport

Serial digital transport control

Link

Serial digital link control

Serial digital link control

Serial physical interface

Physical

Serial physical interface

Host Layers

Device Layers

Link Layer
8b / 10b encoding Scrambles and descrambles data and control words Converts data from transport layer into frames Conduct CRC generation and checking Provides frame flow control

Encoding Concepts
All 32 bit Dwords are encoded for SATA
32 bits data = 40 bits of transmission

Provides sufficient transition density

Guarantees transition (0s and 1s) even if data is 0x00 or 0xFF

Provides an easy way to detect transmission error

Current Running Disparity (CRD)

As each character is encoded a count is maintained of the number of 0s and 1s being transmitted
More 1s than 0s give positive disparity More 0s than 1s gives negative disparity Same number gives neutral disparity

Only valid values of CRD are -1 and 1

Any other value indicates that a transmission error has occurred

CRD+ & CRD- Encoded Characters

8b Character 0x3F

0 0 1 1 1 1 1 1
This 10b Character transmitted when CRD negative This 10b Character transmitted when CRD positive

1 0 1 0 1 1 1 0 0 1
This character

0 1 0 1 0 0 1 0 0 1
This character

6 ones
4 zeros Disparity +2

4 ones
6 zeros Disparity -2

SATA Primitives
Convey real-time state information Control transfer of information between host and device Provide host/device coordination

SATA Primitives
ALIGN Speed negotiation and at least every 256 Dword SYNC Used when in idle to maintain bit synchronization

CONT Used to suppress repeated primitives

SATA Primitives
X_RDY R_RDY

SOF EOF

R_IP
R_OK R_ERR

HOLD HOLDA

SATA Frame Structure

All SATA frames consist of:
A start of frame (SOF) delimiter A payload transport layer information A Cyclic Redundancy Check (CRC) An end of frame (EOF) delimiter

SOF

Payload Data

CRC

EOF

Link Layer Protocol (1)

SYNC SYNC SYNC SYNC SYNC SYNC

Host
SYNC SYNC SYNC SYNC SYNC

Device
SYNC

Link Layer Protocol (2)

X_RDY X_RDY X_RDY X_RDY SYNC SYNC

Host
SYNC SYNC SYNC SYNC SYNC

Device
SYNC

Link Layer Protocol (3)

X_RDY X_RDY X_RDY X_RDY X_RDY X_RDY

Host
SYNC SYNC R_RDY R_RDY R_RDY

Device
R_RDY

Link Layer Protocol (4)

DATA DATA DATA SOF X_RDY X_RDY

Host
R_RDY R_RDY R_RDY R_RDY R_RDY

Device
R_RDY

Link Layer Protocol (5)

DATA DATA DATA DATA DATA DATA

Host
R_RDY R_RDY R_IP R_IP R_IP

Device
R_IP

Link Layer Protocol (6)

WTRM WTRM EOF CRC DATA DATA

Host
R_IP R_IP R_IP R_IP R_IP

Device
R_IP

Link Layer Protocol (7)

WTRM WTRM WTRM WTRM EOF CRC

Host
R_IP R_IP R_IP R_IP R_IP

Device
R_IP

Link Layer Protocol (8)

WTRM WTRM WTRM WTRM WTRM WTRM

Host
R_IP R_IP R_OK R_OK R_OK

Device
R_OK

Link Layer Protocol (9)

SYNC SYNC SYNC SYNC WTRM WTRM

Host
R_OK R_OK R_OK R_OK R_OK

Device
R_OK

Link Layer Protocol (last)

SYNC SYNC SYNC SYNC SYNC SYNC

Host
R_OK R_OK SYNC SYNC SYNC

Device
SYNC

SATA Architectural Model

Host Control Software
Buffer Memory DMA management
Application

Device Control Software Buffer Memory DMA management

Serial digital transport control

Transport

Serial digital transport control

Link

Serial digital link control

Serial digital link control

Serial physical interface

Physical

Serial physical interface

Host Layers

Device Layers

Transport Layer
Responsible for the management of Frame Information Structures (FIS) At the command of Application layer:
Format the FIS Make frame transmission request to Link layer Pass FIS contents to Link layer Receive transmission status from Link layer and reports to Application layer

Frame Information Structure (FIS)

A FIS is a mechanism to transfer information between host and device application layers
Shadow Register Block contents ATA commands Data movement setup information Read and write data Self test activation Unique FIS Type Code

FIS types
FIS TYPE CODE 27h 34h A1h 39h 41h 58h 5Fh 46h Description Direction D H H H H H H H
Register transfer host to device H Register transfer device to host D Set Device bits

DMA Activate
DMA Setup BIST Activate

PIO Setup Data

D D D D D D

Register Host to Device FIS

Byte 3 Dword 0
Features

Byte 2

Byte 1

Byte 0
FIS TYPE (27h) Sector Number Sector Number Sector Count

Command Reserved Cyl High Cyl High (exp) Reserved Cyl Low Cyl Low (exp) Sector Count

Dword 1 Dev/Head Dword 2 Dword 3

Features (exp) Control

Dword 4 Reserved Reserved Reserved Reserved

BIST Activate FIS

Byte 3 0
Reserved

Byte 2
[ TASLFPRV ]

Byte 1
Reserved Data [15:8]

Byte 0
FIS Type 58h Data [7:0]

1 Data [31:24] Data [23:16]

2 Data [31:24] Data [23:16]

Data [15:8]

Data [7:0]

T - Far end transmit only transmit Dwords defined in words 1 & 2 A - No ALIGN transmission (valid only with T) S - Bypass scrambling (valid only with T) L - Far end retimed loopback with ALIGN insertion F - Far end analog loopback P - Transmit primitives defined in words 1 & 2 of the FIS R - Reserved V - Vendor Unique Test Mode other bits undefined

Data FIS
Byte 3 Byte 2 Byte 1 Byte 0
(46h)

Dword 0 Reserved Reserved Reserved FIS TYPE Dword 1 Dword 2

N Dwords of Data Minimum 1 Dword Maximum 2048 Dwords

... Dword N

SATA Architectural Model

Host Control Software
Buffer Memory DMA management
Application

Device Control Software Buffer Memory DMA management

Serial digital transport control

Transport

Serial digital transport control

Link

Serial digital link control

Serial digital link control

Serial physical interface

Physical

Serial physical interface

Host Layers

Device Layers

Command / Application Layer

Defined using a series of state diagrams
Register H D Register D H DMA data in DMA data out

Host command layer may be the same but may only support legacy commands

Completed !!
Any Question? Comments?