Module 5: Digital Input / Output

Digital Signal Controller

TMS320F2833x
Texas Instruments Incorporated
European Customer Training Centre
University of Applied Sciences Zwickau

5-1
 F2833x Block Diagram
Program Bus
ePWM

Boot DMA eCAP

Sectored RAM
ROM 6 Ch.
A(19-0) Flash eQEP
XINTF

DMA Bus
12-bit ADC

D(31-0) Watchdog

PIE
32-bit R-M-W Interrupt CAN 2.0B
32x32 bit Manager
Auxiliary Atomic FPU
Multiplier I2C
Registers ALU
3
Real-Time SCI
32-bit
JTAG Register Bus Timers SPI
Emulation CPU
McBSP
Data Bus
GPIO
5-2
 TMS320F2833x Memory Map
Data Program
0x000000 0x010000
M0 SARAM (1Kw)
0x000400 reserved
M1 SARAM (1Kw) 0x100000
0x000800 XINTF Zone 6 (1Mw)
0x000D00 0x200000
PIE Vectors XINTF Zone 7 (1Mw)
(256 w) 0x300000
0x000E00 reserved
PF 0 (6Kw) FLASH (256Kw) Dual Mapped:
0x002000
L0, L1, L2, L3
0x004000 0x33FFF8 PASSWORDS (8w)
XINTF Zone 0 (4Kw) 0x340000
0x005000 reserved
PF 3 (4Kw) 0x380080
0x006000 ADC calibration data
PF 1 (4Kw) reserved 0x380090 CSM Protected:
0x007000 reserved
PF 2 (4Kw) 0x380400 L0, L1, L2, L3,
0x008000 User OTP (1Kw) FLASH, ADC CAL,
L0 SARAM (4Kw) 0x380800
0x009000 reserved OTP
L1 SARAM (4Kw) 0x3F8000
0x00A000 L0 SARAM (4Kw)
L2 SARAM (4Kw) 0x3F9000
0x00B000 L1 SARAM (4Kw)
L3 SARAM (4Kw) 0x3FA000 DMA Accessible:
0x00C000 L2 SARAM (4Kw)
L4 SARAM (4Kw) 0x3FB000 L4, L5, L6, L7,
0x00D000 L3 SARAM (4Kw) XINTF Zone 0, 6, 7
L5 SARAM (4Kw) 0x3FC000
0x00E000 reserved
L6 SARAM (4Kw) 0x3FE000
0x00F000 Boot ROM (8Kw)
L7 SARAM (4Kw)
0x010000 0x3FFFC0 BROM Vectors (64w)
0x3FFFFF
Data Program
5-3
 F2833x GPIO Pin Block Diagram

Peripheral Peripheral Peripheral

I/O DIR Bit 1 2 3
GPxSET 0 = Input
GPxCLEAR 1 = Output
GPxTOGGLE
GPxDIR
GPxDAT • • 10
01
GPxMUX1
00• •11
Out
GPxMUX2
I/O DAT
Bit (R/W) MUX Control Bits *
In
00 = GPIO
01 = Peripheral 1
10 = Peripheral 2
11 = Peripheral 3
Input
Qualification
GPxPUD
• (GPIO 0-63 only)
GPxQSEL1
GPxQSEL2
Internal Pull-Up GPxCTRL
0 = enable (default GPIO 12-31)
1 = disable (default GPIO 0-11)
Pin

* See device datasheet for pin function selection matrices 5-4

 F2833x GPIO Grouping Overview

GPIO Port A Mux1

Register (GPAMUX1) Input

GPIO Port A
[GPIO 0 to 15] GPIO Port A
Direction Register Qual
(GPADIR)
GPIO Port A Mux2 [GPIO 0 to 31]
Register (GPAMUX2)
[GPIO 16 to 31]

GPIO Port B Mux1 Input

Register (GPBMUX1)
Internal Bus

GPIO Port B
[GPIO 32 to 47] GPIO Port B
Direction Register Qual
(GPBDIR)
GPIO Port B Mux2 [GPIO 32 to 63]
Register (GPBMUX2)
[GPIO 48 to 63]

GPIO Port C Mux1

Register (GPCMUX1)

GPIO Port C
[GPIO 64 to 79] GPIO Port C
Direction Register
(GPCDIR)
GPIO Port C Mux2 [GPIO 64 to 87]
Register (GPCMUX2)
[GPIO 80 to 87]

5-5
 F2833x GPIO Pin Assignment

GPIO - A Multiplex Register GPAMUX1

GPAMUX1 - Bits 00 01 10 11
1,0 GPIO0 EPWM1A - -
3,2 GPIO1 EPWM1B ECAP6 MFSRB
5,4 GPIO2 EPWM2A - -
7,6 GPIO3 EPWM2B ECAP5 MCLKRB
9,8 GPIO4 EPWM3A - -
11,10 GPIO5 EPWM3B MFSRA ECAP1
13,12 GPIO6 EPWM4A EPWMSYNCI EPWMSYNC0
15,14 GPIO7 EPWM4B MCLKRA ECAP2
17,16 GPIO8 EPWM5A CANTXB /ADCSOCA0
19,18 GPIO9 EPWM5B SCITXDB ECAP3
21,20 GPIO10 EPWM6A CANRXB /ADCSOCB0
23,22 GPIO11 EPWM6B SCIRXDB ECAP4
25,24 GPIO12 /TZ1 CANTXB SPISIMOB
27,26 GPIO13 /TZ2 CANRXB SPISOMIB
29,28 GPIO14 /TZ3_/XHOLD SCITXDB SPICLKB
31,30 GPIO15 /TZ4_/XHOLDA SCIRXDB /SPISTEB

5-6
 F2833x GPIO Pin Assignment

GPIO - A Multiplex Register GPAMUX2

GPAMUX2 - Bits 00 01 10 11
1,0 GPIO16 SPISIMOA CANTXB /TZ5
3,2 GPIO17 SPISOMIA CANRXB /TZ6
5,4 GPIO18 SPICLKA SCITXDB CANRXA
7,6 GPIO19 /SPISTEA SCIRXDB CANTXA
9,8 GPIO20 EQEP1A MDXA CANTXB
11,10 GPIO21 EQEP1B MDRA CANRXB
13,12 GPIO22 EQEP1S MCLKXA SCITXDB
15,14 GPIO23 EQEP1I MFSXA SCIRXDB
17,16 GPIO24 ECAP1 EQEP2A MDXB
19,18 GPIO25 ECAP2 EQEP2B MDRB
21,20 GPIO26 ECAP3 EQEP2I MCLKXB
23,22 GPIO27 ECAP4 EQEP2S MFSXB
25,24 GPIO28 SCIRXDA /XZCS6 /XZCS6
27,26 GPIO29 SCITXDA XA19 XA19
29,28 GPIO30 CANRXA XA18 XA18
31,30 GPIO31 CANTXA XA17 XA17

5-7
 F2833x GPIO Pin Assignment

GPIO - B Multiplex Register GPBMUX1

GPBMUX1 - Bits 00 01 10 11
1,0 GPIO32 SDAA EPWMSYNCI /ADCSOCA0
3,2 GPIO33 SCLA EPWMSYNCO /ADCSOCB0
5,4 GPIO34 ECAP1 XREADY XREADY
7,6 GPIO35 SCITXDA XR/W XR/W
9,8 GPIO36 SCIRXDA /XZCS0 /XZCS0
11,10 GPIO37 ECAP2 /XZCS7 /XZCS7
13,12 GPIO38 - /XWE0 /XWE0
15,14 GPIO39 - XA16 XA16
17,16 GPIO40 - XA0/XWE1 XA0/XWE1
19,18 GPIO41 - XA1 XA1
21,20 GPIO42 - XA2 XA2
23,22 GPIO43 - XA3 XA3
25,24 GPIO44 - XA4 XA4
27,26 GPIO45 - XA5 XA6
29,28 GPIO46 - XA6 XA6
31,30 GPIO47 - XA7 XA7

5-8
 F2833x GPIO Pin Assignment

GPIO - B Multiplex Register GPBMUX2

GPBMUX2 - Bits 00 01 10 11
1,0 GPIO48 ECAP5 XD31 XD31
3,2 GPIO49 ECAP6 XD30 XD30
5,4 GPIO50 EQEP1A XD29 XD29
7,6 GPIO51 EQEP1B XD28 XD28
9,8 GPIO52 EQEP1S XD27 XD27
11,10 GPIO53 EQEP1I XD26 XD26
13,12 GPIO54 SPISIMOA XD25 XD25
15,14 GPIO55 SPISOMIA XD24 XD24
17,16 GPIO56 SPICLKA XD23 XD23
19,18 GPIO57 /SPISTEA XD22 XD22
21,20 GPIO58 MCLKRA XD21 XD21
23,22 GPIO59 MFSRA XD20 XD20
25,24 GPIO60 MCLKRB XD19 XD19
27,26 GPIO61 MFSRB XD18 XD18
29,28 GPIO62 SCIRXDC XD17 XD17
31,30 GPIO63 SCITXDC XD16 XD16

5-9
 F2833x GPIO Pin Assignment
GPIO - C Multiplex Register

GPCMUX1 - 00 or 01 10 or 11 GPCMUX2 - 00 or 01 10 or 11
Bits Bits
1,0 GPIO64 XD15 1,0 GPIO80 XA8
3,2 GPIO65 XD14 3,2 GPIO81 XA9
5,4 GPIO66 XD13 5,4 GPIO82 XA10
7,6 GPIO67 XD12 7,6 GPIO83 XA11
9,8 GPIO68 XD11 9,8 GPIO84 XA12
11,10 GPIO69 XD10 11,10 GPIO85 XA13
13,12 GPIO70 XD9 13,12 GPIO86 XA14
15,14 GPIO71 XD8 15,14 GPIO87 XA15
17,16 GPIO72 XD7 17,16 - -
19,18 GPIO73 XD6 19,18 - -
21,20 GPIO74 XD5 21,20 - -
23,22 GPIO75 XD4 23,22 - -
25,24 GPIO76 XD3 25,24 - -
27,26 GPIO77 XD2 27,26 - -
29,28 GPIO78 XD1 29,28 - -
31,30 GPIO79 XD0 31,30 - -

5 - 10
 F2833x GPIO Input Qualification

Input to GPIO and

pin peripheral
Qualification modules

SYSCLKOUT

 Qualification available on ports A & B (GPIO 0 - 63) only

 Individually selectable per pin samples taken
 no qualification (peripherals only)
 sync to SYCLKOUT only
 qualify 3 samples
 qualify 6 samples
 Port C pins are fixed as T T T
‘sync to SYSCLKOUT’ T = qualification period
5 - 11
 F2833x GPIO Input Qualification Registers

GPAQSEL1 / GPAQSEL2 / GPBQSEL1 / GPBQSEL2

31 0
16 pins configured per register

00 = sync to SYSCLKOUT only

01 = qual to 3 samples
10 = qual to 6 samples
11 = no sync or qual (for peripheral only; GPIO same as 00)

GPACTRL / GPBCTRL
31 24 16 8 0
QUALPRD3 QUALPRD2 QUALPRD1 QUALPRD0
B: GPIO63-56 GPIO55-48 GPIO47-40 GPIO39-32
A: GPIO31-24 GPIO23-16 GPIO15-8 GPIO7-0

0x00 no qualification (SYNC to SYSCLKOUT)

0x01 QUALPRD = TSYSCLKOUT * 2
0x02 QUALPRD = TSYSCLKOUT * 4
… … …
0xFF QUALPRD = TSYSCLKOUT * 510 5 - 12
 C2833x GPIO Control Registers

Register Description
GPACTRL GPIO A Control Register [GPIO 0 – 31]
GPAQSEL1 GPIO A Qualifier Select 1 Register [GPIO 0 – 15]
GPAQSEL2 GPIO A Qualifier Select 2 Register [GPIO 16 – 31]
GPAMUX1 GPIO A Mux1 Register [GPIO 0 – 15]
GPAMUX2 GPIO A Mux2 Register [GPIO 16 – 31]
GPADIR GPIO A Direction Register [GPIO 0 – 31]
GPAPUD GPIO A Pull-Up Disable Register [GPIO 0 – 31]
GPBCTRL GPIO B Control Register [GPIO 32 – 63]
GPBQSEL1 GPIO B Qualifier Select 1 Register [GPIO 32 – 47]
GPBQSEL2 GPIO B Qualifier Select 2 Register [GPIO 48 – 63]
GPBMUX1 GPIO B Mux1 Register [GPIO 32 – 47]
GPBMUX2 GPIO B Mux2 Register [GPIO 48 – 63]
GPBDIR GPIO B Direction Register [GPIO 32 – 63]
GPBPUD GPIO B Pull-Up Disable Register [GPIO 32 – 63]
GPCMUX1 GPIO C Mux1 Register [GPIO 64 – 79]
GPCMUX2 GPIO C Mux2 Register [GPIO 80 – 87]
GPCDIR GPIO C Direction Register [GPIO 64 – 87]
GPCPUD GPIO C Pull-Up Disable Register [GPIO 64 – 87]
5 - 13
 C2833x GPIO Data Registers

Register Description
GPADAT GPIO A Data Register [GPIO 0 – 31]
GPASET GPIO A Data Set Register [GPIO 0 – 31]
GPACLEAR GPIO A Data Clear Register [GPIO 0 – 31]
GPATOGGLE GPIO A Data Toggle [GPIO 0 – 31]
GPBDAT GPIO B Data Register [GPIO 32 – 63]
GPBSET GPIO B Data Set Register [GPIO 32 – 63]
GPBCLEAR GPIO B Data Clear Register [GPIO 32 – 63]
GPBTOGGLE GPIO B Data Toggle [GPIO 32 – 63]
GPCDAT GPIO C Data Register [GPIO 64 – 87]
GPCSET GPIO C Data Set Register [GPIO 64 – 87]
GPCCLEAR GPIO C Data Clear Register [GPIO 64 – 87]
GPCTOGGLE GPIO C Data Toggle [GPIO 64 – 87]

5 - 14
 F2833x Clock Module

Watchdog
Module CLKIN C28x
XCLKIN
Core
OSCCLK
X1
• • (PLL bypass)
SYSCLKOUT

MUX
• •
XTAL OSC

1/n
crystal VCOCLK
PLL HISPCP LOSPCP
X2
HSPCLK LSPCLK
SysCtrlRegs.PLLCR.bit.DIV ADC SCI, SPI, I2C,
SysCtrlRegs.PLLSTS.bit.DIVSEL McBSP
All other peripherals
DIVSEL n DIV CLKIN clocked by SYSCLKOUT
0x /4 * 0000 OSCCLK / n * (PLL bypass)
10 /2 0001 OSCCLK x 1 / n
0010 OSCCLK x 2 / n Input Clock Fail Detect Circuitry
11 /1
0011 OSCCLK x 3 / n
* default 0100 OSCCLK x 4 / n PLL will issue a “limp mode”
Note: /1 mode can 0101 OSCCLK x 5 / n clock (1-4 MHz) if input clock is
only be used when removed after PLL has locked.
PLL is bypassed 0110 OSCCLK x 6 / n
0111 OSCCLK x 7 / n An internal device reset will also
1000 OSCCLK x 8 / n be issued (XRSn pin not driven).
1001 OSCCLK x 9 / n
1010 OSCCLK x 10 / n
5 - 15
 F2833x Clock Scaling

SysCtrlRegs.HISPCP
15 - 3 2-0
reserved HSPCLK

ADC
SysCtrlRegs.LOSPCP
15 - 3 2-0
reserved LSPCLK

SCI / SPI /
H/LSPCLK Peripheral Clock Frequency I2C / McBSP
000 SYSCLKOUT / 1
001 SYSCLKOUT / 2 (default HISPCP)
NOTE:
010 SYSCLKOUT / 4 (default LOSPCP)
011 SYSCLKOUT / 6 All Other
100 SYSCLKOUT / 8 Peripherals
101 SYSCLKOUT / 10 Clocked By
110 SYSCLKOUT / 12 SYSCLKOUT
111 SYSCLKOUT / 14

5 - 16
 F2833x Clock Control Unit

SysCtrlRegs.PCLKCR0
15 14 13 12 11 10 9 8
ECANB ECANA MA MB SCIB SCIA reserved SPIA
ENCLK ENCLK ENCLK ENCLK ENCLK ENCLK ENCLK
7 6 5 4 3 2 1 0
SCIC I2CA ADC TBCLK reserved reserved
reserved reserved ENCLK ENCLK ENCLK SYNC

SysCtrlRegs.PCLKCR1
15 14 13 12 11 10 9 8
EQEP2 EQEP1 ECAP6 ECAP5 ECAP4 ECAP3 ECAP2 ECAP1
ENCLK ENCLK ENCLK ENCLK ENCLK ENCLK ENCLK ENCLK
7 6 5 4 3 2 1 0

reserved EPWM6 EPWM5 EPWM4 EPWM3 EPWM2 EPWM1

reserved ENCLK ENCLK ENCLK
ENCLK ENCLK ENCLK

SysCtrlRegs.PCLKCR3
15 - 14 13 12 11 10 9 8 7-0

reserved GPIOIN XINTF DMA CPUTIMER2 CPUTIMER1 CPUTIMER0 reserved

ENCLK ENCLK ENCLK ENCLK ENCLK ENCLK

Module Enable Clock Bit

0 = disable (default) 1 = enable
5 - 17
 Watchdog Timer

 Resets the F2833x if the CPU crashes

 Watchdog counter runs independent of CPU
 If counter overflows, a reset or interrupt is
triggered (user selectable)
 CPU must write correct data key sequence to
reset the counter before overflow
 Watchdog must be serviced or disabled
within 4.37ms after reset (assuming a 30
MHz OSCCLK)
 This time period translates into 645000
instructions, if CPU runs at 150MHz!

5 - 18
 Watchdog Timer Module
SCSR . 0
OSCCLK
/64 111
6 - Bit /32 110 WDOVERRIDE
Free - WDPS
/16 101
WDCR . 2 - 0
/512 • Running /8 100
Counter /4 011 • • •
/2 010 WDCR . 6
CLR 001
WDDIS
000
•
•
WDCNTR . 7 - 0
System
Reset • 8 - Bit Watchdog
WDFLAG

Counter One-Cycle WDCR . 7

Delay
CLR
WDRST
Output •
Pulse
WDCR . 5 - 3 WDCHK 2-0 WDINT
55 + AA SCSR .1
Detector Good Key 3 WDENINT
•• /
•• 3
3
/ Bad WDCR Key
Watchdog 1 0 1
Reset Key WDKEY . 7 - 0
Register
5 - 19
 Watchdog Timer Control Register
Register: SysCtrlRegs.WDCR

WD Flag Bit
Gets set when the WD causes a reset
• Writing a 1 clears this bit
• Writing a 0 has no effect

15 - 8 7 6 5-3 2-0

reserved WDFLAG WDDIS WDCHK WDPS

Logic Check Bits WD Prescale

Write as 101 or reset Selection Bits
Watchdog Disable Bit immediately triggered
Write 1 to disable
(Functions only if WD OVERRIDE
bit in SCSR is equal to 1)

5 - 20
 Resetting the Watchdog

15 - 8 7-0

reserved WDKEY

 WDKEY write values:

0x55 - counter enabled for reset on next 0xAA write
0xAA - counter set to zero if reset enabled
 Writing any other value has no effect
 Watchdog should not be serviced solely in an
ISR
 If main code crashes, but interrupt continues to
execute, the watchdog will not catch the crash
 Could put the 0x55 WDKEY in the main code, and
the 0xAA WDKEY in an ISR; this catches main
code crashes and also ISR crashes
5 - 21
 WDKEY Write Results

Sequential Value Written

Step to WDKEY Result

1 AAh No action
2 AAh No action
3 55h WD counter enabled for reset on next AAh write
4 55h WD counter enabled for reset on next AAh write
5 55h WD counter enabled for reset on next AAh write
6 AAh WD counter is reset
7 AAh No action
8 55h WD counter enabled for reset on next AAh write
9 AAh WD counter is reset
10 55h WD counter enabled for reset on next AAh write
11 23h No effect; WD counter not reset on next AAh write
12 AAh No action due to previous invalid value
13 55h WD counter enabled for reset on next AAh write
14 AAh WD counter is reset

5 - 22
System Control and Status Register

Register: SysCtrlRegs.SCSR

WD Override (protect bit)

Protects WD from being disabled
0 = WDDIS bit in WDCR has no effect (WD cannot be disabled)
1 = WDDIS bit in WDCR can disable the watchdog
• This bit is a clear-only bit (write 1 to clear)
• The reset default of this bit is a 1

15 - 3 2 1 0

reserved WDINTS WDENINT WDOVERRIDE

WD Interrupt Status WD Enable Interrupt

(read only)
0 = WD generates a DSP reset
0 = active 1 = WD generates a WDINT interrupt
1 = not active

5 - 23
 Low Power Modes

Low Power CPU Logic Peripheral Watchdog PLL /

Mode Clock Logic Clock Clock OSC
Normal Run on on on on

IDLE off on on on

STANDBY off off on on

HALT off off off off

See device datasheet for power consumption in each mode

5 - 24
 Low Power Mode Control Register 0
Register: SysCtrlRegs.LPMCR0
Watchdog Interrupt 000000 = 2 OSCCLKs
wake device from 000001 = 3 OSCCLKs
STANDBY Wake from STANDBY
0 = disable (default) GPIO signal qualification *
1 = enable 111111 = 65 OSCCLKS (default)

15 14 - 8 7-2 1-0
WDINTE reserved QUALSTDBY LPM0

Low Power Mode Selection

Low Power Mode Entering 00 = Idle (default)
1. Set LPM bits 01 = Standby
2. Enable desired exit interrupt(s) 1x = Halt
3. Execute IDLE instruction
4. The Power down sequence of the hardware
depends on LP mode

* QUALSTDBY will qualify the GPIO wakeup signal in series with the GPIO port qualification.
This is useful when GPIO port qualification is not available or insufficient for wake-up purposes.
5 - 25
 Low Power Mode Exit

Exit
Interrupt RESET GPIO Watchdog Any
or Port A Interrupt Enabled
Low Power XNMI Signal Interrupt
Mode

IDLE yes yes yes yes

STANDBY yes yes yes no

HALT yes yes no no

5 - 26
 GPIO Low Power Wakeup Select

Register: SysCtrlRegs.GPIOLPMSEL
31 30 29 28 27 26 25 24

GPIO31 GPIO30 GPIO29 GPIO28 GPIO27 GPIO26 GPIO25 GPIO24

23 22 21 20 19 18 17 16
GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 GPIO18 GPIO17 GPIO16

15 14 13 12 11 10 9 8

GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8

7 6 5 4 3 2 1 0
GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0

Wake device from

HALT and STANDBY mode
(GPIO Port A)
0 = disable (default)
1 = enable
5 - 27
 Lab 5_1: “Binary Counter” at 4 LEDs

Objective:
• Display the 4 least significant bits of a counter variable at
LED LD1(GPIO9), LD2(GPIO11), LD3(GPIO34) and
LD4(GPIO49) of the Peripheral Explorer Board.
• Increment variable “counter” every 100 milliseconds
• Use a software delay loop to generate the interval of 100
milliseconds
0000 Project - Files :
1. C - source file “Lab5_1.c”
0001 2. Start assembly code file:
“DSP2833x_CodeStartBranch.asm”
0010 2. Register Variable Definition File:
“DSP2833x_GlobalVariableDefs.c”
… 3. Linker Command File:
1111 “28335_RAM_lnk.cmd”
“DSP2833x_Headers_nonBIOS.cmd”
4. Runtime Library “rts2800_fpu32.lib”
5 - 28
 “DSP2833x_GlobalVariableDefs.c”

• Definition of global variables for all memory mapped

peripheral registers based on predefined structures
• Master Header File is “DSP2833x_Device.h”
• Example GpioDataRegs:
volatile struct GPIO_DATA_REGS GpioDataRegs;
• This structure variable combines all registers, which
belong to this peripheral group, e.g.:
GpioDataRegs.GPADAT
• Each register is declared as a union to allow 32-bit -
(“all”) and single bit field - accesses (“bit”), e.g.:
GpioDataRegs.GPADAT.bit.GPIO9 = 1;
GpioDataRegs.GPADAT.all = 0x0000FFFF;

• Steps to be done are:

1. Add “DSP2833x_GlobalVariableDefs.c” to project
2. Include “DSP2833x_Device.h” into your C-code
5 - 29
 “Lab 5_1 Register usage”

Registers involved in LAB 5_1:

• Core Initialisation:
• Watchdog - Timer - Control : WDCR
• PLL Clock Register : PLLCR
• High Speed Clock Pre-scaler : HISPCP
• Low Speed Clock Pre-scaler : LOSPCP
• Peripheral Clock Control : PCLKCRx
• System Control and Status : SCSR

• Access to LED‘s (GPIO9, GPIO11,GPIO34,GPIO49):

• GPA and GPB Multiplex Register:
• GPAMUX1, GPAMUX2, GPBMUX1, GPBMUX2
• GPA and GPB Direction Register:
• GPADIR and GPBDIR
• GPA and GPB Data Register:
• GPASET, GPACLEAR, GPBSET, GPBCLEAR 5 - 30
 Lab Exercise 5_2

Modify the C -source – code to:

• switch 4 LEDs at GPIO9, GPIO11, GPIO34

and GPIO49 sequentially on and off
• use a software time delay from Lab5_1
GPIO9 GPIO11 GPIO34 GPIO49

Step 1

Step 2 Step 6

Step 3 Step 5
Step 4
5 - 31
 Lab 5_3: Digital Input (GPIO 15...12)
Objective:
• a 4 bit hex encoder connected to GPIO15…GPIO12
• 4 LED‘s connected to GPIO9, GPIO11, GPIO34 and
GPIO49
• read the status of encoder and display it at the LEDs

Project - Files :
1. C - source file: “Lab5_3.c”
2. Register Definition File:
“DSP2833x_GlobalVariableDefs.c”
3. Linker Command File:
“28335_RAM_lnk.cmd”
4. Runtime Library: “rts2800_fpu32.lib”

5 - 32
 Lab 5_4: Digital In- and Output

• Mix between Lab5_1 and LAB5_3:

• change the loop – speed of Lab5_1 depending of

the status of the hex – encoder.
• If hex – encoder reads “0000”, set the time period
for the LED update to approximately 100 ms.
• If hex - encoder reads “1111”, set the time period for
the LED update to approximately 1.6 seconds.
• Adjust the period for all other encoder values
accordingly.

5 - 33
 Lab 5_5: Start - /Stop Control

• Add a start/stop function to Lab5_4:

• Peripheral Explorer Board Pushbuttons:

• PB1 (GPIO17) to start/restart control code
• PB2 (GPIO48) to stop/suspend control code

• If PB1 is pushed, LED counting should start / resume

• If PB2 is pushed, LED counting should stop.

5 - 34