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Timing Analysis & Debug (Counter Design) Nishanth

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Nishanth Gowda
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172 views

Timing Analysis & Debug (Counter Design) Nishanth

Uploaded by

Nishanth Gowda
Copyright
© © All Rights Reserved
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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TIMING ANALYSIS & DEBUG

Inputs to Tempus

 counter_netlist.v - Gate-level netlist output after synthesis.

 counter_sdc.sdc - Constraint file generated during synthesis.

 counter.view - The implementation view definitions listed in this MMMC file.

 gsclib045_tech.lef, gsclib045_macro.lef - LEF files used in physical design.

 slow_vddIvO basicCells.lib and fast_vddlv0 basicCells.lib - Timing libraries.

 SPEF – Parasitic Data

will be running a Tempus-style timing analysis inside of Innovus.


• Let us rerun the previous session of Place & Route inside the STA directory instead of using a saved session

$ cd counter_design/STA

$ innovus -stylus -files runPnR.tel


At the end of this session, the design is routed and timing analyzed.

A screenshot of runPnR.tel is shown here.


2. Set the timing analysis mode :
set_db timing_analysis_type ocv

3. Run setup-and-hold timing analysis :


time_ design -post_route

Timing summary ,design doesn’t have any violating paths in setup mode
run the hold check using the command:
time_design -post_route -hold

• There are a lot of hold violations in the design. We fix all of them in Tempus.

4. If the graphical interface is not open, start it using the following command:
gui show
Run timing analysis using the Timing - Debug Timing menu.

a. Select hold in the Check Type field.


b. Click OK.
The Timing Debug window opens

C .Right-click on path #1 in the Path List and select Show Timing Path Analyzer
Timing Path Analyzer window

6. Save the design including the SPEF, DEF, and the libraries, by entering:
write_db -rc_extract -def postRoute

Keep this session open if you would like for debugging purposes. You can close it later.
Run an Independent Timing Analysis in Tempus

1. Start Tempus independently:


tempus –stylus

2. Load the Innovus database into Tempus using the following command:
read_db -physical_data postRoute

This loads the entire design along with the physical layout.

Open the Layout tab click the plus sign to see other available tabs to confirm that the same layout from Innovus is also shown
here in Tempus.

Once the design is loaded successfully, then generate reports

3. Check the analysis coverage using the following command:


report_analysis_coverage

4. View the list of all constraint violations using the following command:
report_constraint -all_violators
5. Report the worst slack time for setup and hold, respectively, using the following commands:
report_timing -late report_timing –early

6. Generate timing histograms using the following commands:


report_timing -early -max_paths 100 -output_format gtd > early.mtarpt read_timing_debug_report early.mtarpt

7. Open the Analysis tab (click the plus sign to see other available tabs)

After the timing analysis is done, you can see the histogram for the hold analysis.

Browse through the Path List with Startpoint Pin as rst, right-click on the path, and select Show Timing Path Analyzer.
will see the Timing Path Analyzer window.

8.In the Timing Path Analyzer window, select the rst pin and right-click and select Interactive ECO/ - Add Repeater

The Interactive ECO window opens, which will allow you to add repeaters.
9. In the Interactive ECO window:
a. Click Get Selected to populate the net information, or just enter rst.

c. Choose early from the Evaluation Type.


d. Click Eval All to choose which buffer is suitable for the path that adds more delay and reduces the hold slack.
From the evaluation list, we can observe that Slack can be reduced to a maximum extent to -0.0956 with the cell BUFX2.

Add only BUFX* cells to fix the timing violation, do not add any CLKBUFX* cells in the design.

e. Now, select the BUFX2 cell in the Interactive ECO.

f. Click Eval Only


10. Click Apply.
11. Rerun the timing report using the below icon from the Analysis window and compare the WNS.

a. Click the load icon from the Report Files field


The Display/Generate Timing Report window appears.

b. Choose the Timing Report File early.mtarpt.


c. Select hold from Check Type.
d. Click OK.
12. Notice the improvement in timing using the below screenshots.Notice the improvement in the WNS in the Analysis window
13. As we can see, the Slack is still negative (-0.096), and we need to add a buffer on the same net of the pin rst, until we get the
Zero/Positive Slack for the pin rst.

14. So, In the Analysis window, select the rst pin and right-click again on the path, and select Show Timing Path Analyzer.

15. Repeat Steps 8, 9, and 10 again by selecting the first path of the rst pin and choosing Add Repeater from the Timing Path
Analyzer window.

Click Eval all and choose the buffer cell (BUFX*).

Repeat Steps 7, 8, 9 and 10 again by selecting the first path of the rst pin from the Analysis window and choosing Add Repeater
from the Timing Path Analyzer window.

ensure that if you have the area constraint or less area is present in your design, then go for the cell, which adds moderate delay
with a lesser area overhead.

Similarly, fix the remaining timing violations. As a result, it will show zero failing paths in the final timing report, as shown in the
screenshot

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