Introduction to IC Technology and

Fabrication Process
 VLSI Design Flow
 Oxidation
 Lithography
 Diffusion
 Ion Implantation
 Metallization
 Encapsulation
 Probe Testing
 Integrated Resistors and Capacitors
VLSI Design Flow
VLSI Design Flow (Design Entry)
User can enter a design with a schematic editor or any other
text based software tool, a hardware description language
(VHDL or Verilog).
Schematic Entry
It provides a graphical interface for design entry. A design
can be build by a user with individual gates or he can
combine gates to create functional blocks.
HDL Entry
This entry supports mixed level description where gate and
netlist constructs both are used along with functional
descriptions.
VLSI Design Flow (Functional Simulation)

 It is the process where the logic in the design is checked

before user implements it in a device. As the timing
information is not available at this early stage of design
flow, functional simulator test the logic of the design
using unit delays.
VLSI Design Flow (Logic Synthesis)
 Here logic synthesis tool is used which produces Netlist
(textual information) from synthesis process. Logic cells
and their interconnections are described in detail in the
Netlist. Netlist is an EDIF (Electronic Design Interchange
Format) file.
 Thus during synthesis behavioral information in the HDL
file is translated into structural netlist.
VLSI Design Flow (Prelayout Simulation)
 This is required for verification of a circuit design through
software programs. Here stimuli is applied to design
over a specific time period and recording, analyzing the
respective response from the model.
VLSI Design Flow (Floor Planner)

 The main function of floor planner is to estimate the

required chip area that will be used for each standard
cell or module of the design. It is responsible for
performance improvement of the design. Floor planner
is a tool that lets user generate and edit hierarchical floor
plans.
VLSI Design Flow (Place and Route)
 After design mapping, flow engine places and routes the
design. All logic blocks, including the Configurable Logic
Blocks (CLB) and Input-Output Blocks (IOB) are
assigned specific locations on the die at place stage.
 In the route stage, the logic blocks are assigned,
particular interconnect elements on die.
VLSI Design Flow (Post Layout Simulation)

 After physical place and route, this simulation is carried

out. While carrying out this simulation propagation
delays of logic cells and interconnection delays of
interconnect are taken into account. If post layout
simulation results fulfill the design specifications,
designer can proceed for chip finishing part.
VLSI Design Flow (Physical Verification)

 After placement and routing and full custom editing

physical verification is carried out. It is the process of
interpreting the physical layout data to determine
whether it confirms to the electrical design rules, physical
design rules and source schematic. Design Rule Check
(DRC) , Electrical Rule Check (ERC), Antenna check
and short circuit check are the processes which comes
under physical verification.
VLSI Design Flow (Testing)
 During production of chips, it is necessary to have some
sort of built-in tests for designed system which
continuously tests the system over long period of time.
Chip will fail because of some electrical or mechanical
problems that will usually show up with such testing
procedure.
VLSI Design Flow (Chip Fabrication)

 Before submitting design for fabrication, input-output

pads should be included in the design and its
connectivity should be verified.
 Then appropriate package selection for the design and
selecting bonding plan for the package is required.
Details of how each pad of design is connected to each
pin of package is required.
Wafer Preparation

The silicon ingot is grown and

individual wafers are sliced.
Oxidation

 Oxidation refers to the chemical process of silicon reacting

with oxygen to form silicon dioxide (SiO2).

 To speed up the reaction, it is necessary to use special high

temperature (e.g. 1000-1200oC) ultra clean furnaces.
 Specially filtered air is circulated in the processing area, and all
personnel must wear special lint-free clothing.
 The oxygen used in the reaction can be introduced either as a
high purity gas (in a process referred to as dry oxidation) or as
steam (for wet oxidation).
 Oxidation
 It has dielectric constant of about 3.9 and can be used to form excellent
capacitors.
 Silicon dioxide serves as an effective mask against many impurities,
allowing the introduction of dopants into the silicon only in regions that
are not covered with oxide.
 Silicon dioxide is thin transparent film, and the silicon surface is highly
reflective.
 Lithography
 Lithography is a process used to transfer a pattern to layer on the chip.
Similar to Printing Process.

 Spin on photoresist (about 1 mm thickness)

 Photoresist is a light-sensitive organic polymer

 Positive Photoresist: Softens where exposed to light

 Negative Photoresist: Hardens where exposed to light

 The patterned photo resist layer can be used as a effective masking

layer to protect materials below from the wet chemical etching or
reactive ion etching.

 After etching steps, the photo resist is stripped away leaving behind
a permanent pattern, an image of the photo mask, on the wafer
surface.
Diffusion

 Diffusion is the process by which atoms move from a high

concentration region to a low concentration region through the
semiconductor crystal.
 In fabrication, diffusion is a method by which to introduce
impurity atoms (dopants) into silicon to change its resistivity.
 The rate at which dopants diffuse in silicon is a strong function
of temperature.
 Thus, for speed, diffusion of impurities is carried out at high
temperatures (10000C -12000C) to obtain the desired doping
profile.
Diffusion

 When the wafer is cooled to room temperature, the impurities

are essentially “frozen” in position.
 The diffusion process is performed in furnaces similar to those
used for oxidation.
 The depth to which the impurities diffuse depends on both the
temperature and the time allocated.
 By diffusing boron into an n-type substrate a pn junction
(diode) is formed.
Ion Implantation
 An ion implanter produces ions of the desired dopant,
accelerates them by electric field, and allows them to strike the
semiconductor surface.
 The ions become embedded in the crystal lattice.
 The depth of penetration is related to the energy of the ion
beam, which can be controlled by the accelerating field voltage.
 Since both voltage and current can be accurately measured
and controlled, ion implantation results in much more accurate
and reproducible impurity profiles that can be obtained by
diffusion.
Ion Implantation
 In addition ion implantation can be performed at room temperature.
Ion implantation is normally used when accurate control of the
doping profile is essential for device operation.
 Ions are accelerated by energies between 20kV to 250kV.
Metallization
 The purpose of metallization is to interconnect the various
components to form the desired integrated circuit.
 Metallization involves the initial deposition of a metal over the entire
surface of the silicon.
 The required interconnection pattern is then selectively etched.
 The metal layer is normally deposited via a sputtering process.
 Aluminium is used for metallization of most IC’s as it offers several
advantages
 It is relatively a good conductor
 It is easy to deposit Aluminium films using Vacuum Deposition
 Aluminium forms good mechanical bond with Silicon.
Probe Testing
 This testing is product specific to data sheet or customer
requirements.
 This test of the wafer has been primarily a room temperature test.
However, there is a trend to raise the substrate temperature to 50°C.
 Each whole die on the wafer is tested. The probe machine moves the
wafer to a location under a set of probe needles.
 The probe needles are lined up with the bonding pads of the first die
to be tested.
 The needles are lowered onto the die (or the die is raised to come into
contact with the needles) and that die is tested.
 The cycle is repeated until all of the whole dice on the wafer are
tested.
 The dice that fail the test are identified, usually with a drop of ink.
 Packaging (Encapsulation)
 A finished silicon wafer may contain several hundred or more
finished circuits or chips.
 Each chip may contain from 10 to 108 or more transistors in a
rectangular shape, typically between 1mm and 10 mm on a side.
 The circuits are first tested electrically using in automatic probing
station.
 Fine gold wires are normally used to connect the pins of the
package to the metallization pattern on the die.
 Finally the package is sealed using plastic or epoxy under vaccum
or in an inert atmosphere.
Integrated Resistors
 Resistors in integrated form are not very precise.
 They can be made from various diffusion regions.
 The basic technique for obtaining a resistor in integrated
circuit is by utilizing the bulk resistance of a defined volume of
semiconductor region.
 Four different types of resistors that can be fabricated in MOS
process are namely

Diffused resistor, Epitaxial resistor, pinched resistor and thin

film resistor.
Integrated Resistors
Integrated Capacitors
 Three types of capacitor structures are available in CMOS process.
MOS , Interpoly (MIM-metal insulator metal ), Junction capacitor

MOS capacitor:
 The MOS gate capacitance is basically the gate to source
capacitance of a MOSFET.
 The capacitance value is dependent on the gate area.
 This capacitor exhibits a large voltage dependence. To eliminate
this problem, an additional n+ implant is required to form at the
bottom plate of the capacitor.
Integrated capacitors

Interpoly capacitor:
 The interpoly capacitor exhibits near ideal characteristics but
at the expense of the inclusion of a second poly silicon layer to
the CMOS process.
 Since the capacitor is placed on top of the thick field oxide,
parasitic effects are kept to a minimum.
Integrated capacitors

Junction capacitor:
 Any PN junction under reversed bias produces a depletion
region that acts as a dielectric between the P and N regions.
 This type of capacitor is often used as a varactor for tuning
circuits.
 This capacitor works only with reverse bias voltages.
Integrated capacitors