UNIT I

STICK DIAGRAMS
 INTRODUCTION

• Objectives:
– To know MOS layers
– To understand the stick diagrams
– To learn design rules
– To understand layout and symbolic diagrams

• Outcome:
– At the end of this, will be able draw the stick
diagram, layout and symbolic diagram for simple
MOS circuits

UNIT – I - Stick and Layout Diagrams

 MOS LAYERS

UNIT – I - Stick and Layout Diagrams

 STICK DIAGRAMS

• Objectives:
– To know what is meant by stick diagram.
– To understand the capabilities and limitations of
stick diagram.
– To learn how to draw stick diagrams for a
given MOS circuit.

• Outcome:
– At the end of this module the students will be able
draw the stick diagram for simple MOS circuits.

UNIT – I - Stick and Layout Diagrams

 STICK DIAGRAMS

• VLSI design aims to translate circuit concepts

onto silicon.
• Stick diagrams are a means of capturing
topography and layer information using simple
diagrams.
• Stick convey layer information
diagrams
through codes (or monochrome
color as an interface between symbolic
• Acts
encoding).
circuit and the actual layout.
UNIT – I - Stick and Layout Diagrams
 STICK DIAGRAMS

• Does show all components/vias.

– Via is used to connect higher level metals from metal
connection
• It shows relative placement of
components.
• Goes one step closer to the layout
• Helps plan the layout and routing

A stick diagram is a cartoon of a layout.

UNIT – I - Stick and Layout Diagrams

 STICK DIAGRAMS

• Does not show

– Exact placement of components
– Transistor sizes
– Wire lengths, wire widths, tub boundaries
– Any other low level details such as
parasitics

UNIT – I - Stick and Layout Diagrams

Standard Cell Layout Methodology

A simple method for finding the optimum gate ordering is the Euler-path method: Simply
find a Euler path in the pull-down network graph and a Euler path in the pull-up network
graph with the identical ordering of input labels, i.e., find a common Euler path for both
graphs.

The Euler path is defined as an uninterrupted path that traverses each edge (branch) of
the graph exactly once.
Finding an Euler’s Path

Computer Algorithms:
• It is relatively easy for a computer to consider all possible arrangements of
transistors in search of a suitable Euler path.
This is not so easy for the human designer.

One Human Algorithm

• Find a path which passes through all n-transistors exactly once.
• Express the path in terms of the gate connections.
• Is it possible to follow a similarly labelled path through the p-transistors?

 Yes – you’ve succeeded.

 No – try again (you may like to try a p path first this time)
Finding an Euler’s Path

Vp

x Vertex b c
x

Edge a

Out

y
y c
Vertex a

Gnd
Euler Path
Stick Diagrams

Stick Diagrams (SD)

• VLSI design aims to translate circuit concepts onto silicon.

• stick diagrams are a means of capturing topography and layer information

using simple diagrams.

• Stick diagrams convey layer information through colour codes (or

monochrome encoding).

• Acts as an interface between symbolic circuit and the actual layout.

Stick Diagrams

Stick Diagrams;

 Does show all components/vias.

 It shows relative placement of components.
 Goes one step closer to the layout
 Helps plan the layout and routing

Stick Diagrams Does not show

•Exact placement of components

•Transistor sizes
•Wire lengths, wire widths, tub boundaries.
•Any other low level details such as parasitics.
Stick Diagrams

Metal

poly

ndiff

pdiff
Can also draw
in shades of
gray/line style.
Stick Diagrams
 STICK DIAGRAMS

Stick Diagrams – Notations

Metal 1

poly

ndif

f
Can also draw
in shades of
pdif gray/line style.
Buried Contact

f
Contact Cut
UNIT – I - Stick and Layout Diagrams
STICK DIAGRAMS

NMOS ENCODING
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STICK DIAGRAMS

CMOS
ENCODING

UNIT – I - Stick and Layout Diagrams

 STICK DIAGRAMS

Stick Diagrams – Some Rules

Rule 1:
When two or more ‘sticks’ of the same type cross or touch
each other that represents electrical contact.

UNIT – I - Stick and Layout Diagrams

 STICK DIAGRAMS

Stick Diagrams – Some Rules

Rule 2:
When two or more „sticks‟ of different type cross or touch each
other there is no electrical contact.
(If electrical contact is needed we have to show the connection
explicitly)

UNIT – I - Stick and Layout Diagrams

 STICK DIAGRAMS

Stick Diagrams – Some Rules

Rule 3:
When a poly crosses diffusion it represents a transistor.

Note: If a contact is shown then it is not a transistor.

UNIT – I - Stick and Layout Diagrams
 STICK DIAGRAMS

Stick Diagrams – Some Rules

Rule 4:
In CMOS a demarcation line is drawn to avoid touching of p-diff
with n-diff. All PMOS must lie on one side of the line and all
NMOS will have to be on the other side.

UNIT – I - Stick and Layout Diagrams

 STICK DIAGRAMS

Examples of Stick Diagrams

Vdd = 5V Vdd = 5V

pMOS
Vin Vout Vin Vout
nMOS

UNIT – I - Stick and Layout Diagrams

 STICK DIAGRAMS

Examples of Stick Diagrams

VDD
VDD
X

x x x
x X

Gnd Gnd

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 STICK DIAGRAMS

Examples of Stick Diagrams

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 STICK DIAGRAMS

Examples of Stick Diagrams

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 STICK DIAGRAMS

Examples of Stick Diagrams

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 STICK DIAGRAMS

Examples of Stick Diagrams

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Example
Example
Example
Example
Example
Example
Example
Example
Example
Example
Example
Example
Example
Example 2
Example 3
Example 3
 DESIGN RULES

• Why we use design rules?

– Interface between designer and process engineer

• Historically, the process technology referred to the

length of the silicon channel between the source and
drain terminals in field effect transistors.
• The sizes of other features are generally derived as
a ratio of the channel length, where some may be
larger than the channel size and some smaller.
– For example, in a 90 nm process, the length of the channel may be 90
nm, but the width of the gate terminal may be only 50 nm.

UNIT – I - Stick and Layout Diagrams

DESIGN RULES

UNIT – I - Stick and Layout Diagrams

 DESIGN RULES

• Allow translation of circuits (usually in stick

diagram or symbolic form) into actual
geometry in silicon
• Interface between circuit designer and
fabrication engineer
• Compromise
– designer - tighter, smaller
– fabricator - controllable, reproducible

UNIT – I - Stick and Layout Diagrams

 DESIGN RULES

• Design rules define ranges for features

– Examples:
• min. wire widths to avoid breaks
• min. spacing to avoid shorts
• minimum overlaps to ensure complete overlaps
– Measured in microns
– Required for resolution/tolerances of masks

• Fabrication processes defined by minimum channel

width
– Also minimum width of poly traces
– Defines “how fast” a fabrication process is

UNIT – I - Stick and Layout Diagrams

 DESIGN RULES

• Two major approaches:

– “Micron” rules: stated at micron resolution.
–  rules: simplified micron rules with
limited scaling attributes.
• Design rules represents a tolerance which insures
very high probability of correct fabrication
– scalable design rules: lambda parameter
– absolute dimensions (micron rules)

UNIT – I - Stick and Layout Diagrams

 DESIGN RULES

“Micron” rules

• All minimum sizes and spacing specified

in microns.
• Rules don't have to be multiples of λ.
• Can result in 50% reduction in area over
λ based rules
• Standard in industry.

UNIT – I - Stick and Layout Diagrams

 DESIGN RULES

Lambda-based Design Rules

• Lambda-based (scalable CMOS) design rules define

scalable rules based on  (which is half of the
minimum channel length)

– classes of MOSIS SCMOS rules: SUBMICRON,

DEEPSUBMICRON

• Stick diagram is a draft of real layout, it serves as an

abstract view between the schematic and layout.

UNIT – I - Stick and Layout Diagrams

 DESIGN RULES

Lambda-based Design Rules

• Circuit designer in general want tighter, smaller layouts
for improved performance and decreased silicon area.
• On the other hand, the process engineer wants design
rules that result in a controllable and reproducible
process.
• Generally we find there has to be a compromise for a
competitive circuit to be produced at a reasonable cost.
• All widths, spacing, and distances are written in the
form
•  = 0.5 X minimum drawn transistor length

UNIT – I - Stick and Layout Diagrams

 Gate Length at Present

Physical gate length of only one

nanometer, this latest transistor, made
from a combination of molybdenum
disulfide and carbon nanotubes
 DESIGN RULES
Lambda-based Design Rules
• Design rules based on single parameter, λ
• Simple for the designer
• Wide acceptance
• Provide feature size independent way of setting
out mask
• If design rules are obeyed, masks will produce working
circuits
• Minimum feature size is defined as 2 λ
• Used to preserve topological features on a chip
• Prevents shorting, opens, contacts from slipping out of
area to be contacted
UNIT – I - Stick and Layout Diagrams
 DESIGN RULES

Design Rules – Reality

• Manufacturing processes have limitations in
inherent accuracy and repeatability

• Design rules specify geometry of masks that

provide reasonable yield

• Design rules are determined by experience

UNIT – I - Stick and Layout Diagrams

 DESIGN RULES

Problems in Manufacturing
• Photoresist shrinking / tearing
• Variations in material deposition
• Variations in temperature
• Variations in oxide thickness
• Impurities
• Variations between lots
• Variations across the wafer

UNIT – I - Stick and Layout Diagrams

 DESIGN RULES
Problems in Manufacturing
• Variations in threshold voltage
– oxide thickness
– ion implantation
– poly variations
• Diffusion - changes in doping (variation in R, C)
• Poly, metal variations in height and width
• Shorts and opens
• Via may not be cut all the way through
• Undersize via has too much resistance
• Oversize via may short
UNIT – I - Stick and Layout Diagrams
 DESIGN RULES

Advantages of Generalized Design

Rules
• Ease of learning because they are
scalable, portable, durable

• Long-levity of designs that are simple, abstract and

minimal clutter

• Increased designer efficiency

• Automatic translation to final layout

UNIT – I - Stick and Layout Diagrams
 DESIGN RULES
• Minimum width of PolySi and diffusion line 2
• Minimum width of Metal line 3 as metal lines run over a
more uneven surface than other conducting layers to ensure
their continuity

Metal

Diffusion


  Polysilicon

UNIT – I - Stick and Layout Diagrams

 DESIGN RULES
• PolySi – PolySi space 2
• Metal - Metal space 2
• Diffusion – Diffusion space 3 To avoid the possibility of
their associated regions overlapping and conducting
current

Metal

Diffusion

  Polysilicon

UNIT – I - Stick and Layout Diagrams

 DESIGN RULES
• Diffusion – PolySi space  To prevent the lines overlapping
to form unwanted capacitor
• Metal lines can pass over both diffusion and polySi without
electrical effect. Where no separation is specified, metal
lines can overlap or cross

Metal

Diffusion

UNIT – I - Stick and Layout Diagrams

 DESIGN RULES
• Metal lines can pass over both diffusion and polySi without
electrical effect
• It is recommended practice to leave  between a metal edge
and a polySi or diffusion line to which it is not electrically
connected

Metal


Polysilicon

UNIT – I - Stick and Layout Diagrams

 DESIGN RULES

• Recall

– poly-poly spacing 2

– diff-diff spacing 3 (depletion regions tend to spread

outward)

– metal-metal spacing 2

– diff-poly spacing 

UNIT – I - Stick and Layout Diagrams

 DESIGN RULES
Contact Cut
• Metal connects to polySi/diffusion by contact cut.
• Contact area: 2  X 2 
• Metal and polySi or diffusion must overlap this contact
area by l so that the two desired conductors encompass the
contact area despite any mis-alignment between
conducting layers and the contact hole

4

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 DESIGN RULES

Contact Cut
• Contact cut – any gate: 2  apart
• Why? No contact to any part of the gate.

4

2

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 DESIGN RULES
Contact Cut
• Contact cut – contact cut: 2  apart
• Why? To prevent holes from merging.

2

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DESIGN RULES

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 DESIGN RULES

3
6

6

2
2

All device mask dimensions are based on multiples of , e.g., polysilicon minimum
width = 2. Minimum metal to metal spacing = 3

UNIT – I - Stick and Layout Diagrams

 DESIGN RULES
Thinox

Metal 1
n-diffusion p-diffusion
3λ
2λ
3λ 3λ
2λ 3λ

Metal 2
2λ
4λ
2λ
2λ 4λ
Polysilicon
4λ

UNIT – I - Stick and Layout Diagrams

 DESIGN RULES

• Wells must surround transistors by 6 

– Implies 12  between opposite transistor
flavors
– Leaves room for one wire track

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 DESIGN RULES

• A wiring track is the space required for a wire

– 4  width, 4  spacing from neighbour = 8 
pitch
• Transistors also consume one wiring track

UNIT – I - Stick and Layout Diagrams

 LAYOUT
S
• Layer Types
– p-substrate
– n-well
– n+
– p+
– Gate oxide
– Gate (polysilicon)
– Field Oxide
• Insulated glass
• Provide electrical isolation

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 LAYOUT
S

N+ N+

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 LAYOUT
S
Top view of the FET pattern

NMOS NMOS PMOS PMOS

n+ n+ n+ n+ p+ p+ p+ p+

n-well

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 LAYOUT
S
General Layout
Vp
Geometry
Shared drain/
source

Individual Shared Gates

Transistors

Gnd

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 LAYOUT
S
Metal Interconnect Layers
• Metal layers are electrically isolated from each other
• Electrical contact between adjacent conducting layers requires contact cuts
and vias
Ox3
Via
Metal2

Active Ox2
contact
Metal1
Ox1

n+ n+ n+ n+

p-substrate

UNIT – I - Stick and Layout Diagrams

 LAYOUT
S
Interconnect Layout Example
Gate contact

Metal1

Metal2
M
e
t
a
l
1
M
O
S

A
c
t
i
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v
 LAYOUT
S
Designing MOS
Arrays
A B C
x y

A B C

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 LAYOUT
S
Parallel Connected MOS
Patterning
A x B x
A B

X X X
y
y

X X
A B
A B
X X

y y
UNIT – I - Stick and Layout Diagrams
 LAYOUT
S
Basic Gate Design
• Both the power supply and ground are routed using the Metal
layer
• n+ and p+ regions are denoted using the same fill pattern. The
only difference is the n-well
• Contacts are needed from Metal to n+ or p+

UNIT – I - Stick and Layout Diagrams

 LAYOUT
S
The CMOS NOT
Gate
Vp Contact Vp
Cut X n-well

X
x x
x X

X
Gnd

Gnd

UNIT – I - Stick and Layout Diagrams

 LAYOUTS
The CMOS NOT
Gate

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 LAYOUT
S
The CMOS NOT
Gate Vp
Vp

X X

x x

X X

Gnd
x Gnd
x

UNIT – I - Stick and Layout Diagrams

 LAYOUT
S
The CMOS NAND Gate

Vp Vp

X X X
a .b

Gnd
a .b
a b
X X

a b
Gnd

UNIT – I - Stick and Layout Diagrams

 LAYOUTS
The CMOS NAND Gate

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 LAYOUT
S
The CMOS NOR Gate

Vp
Vp

X X

a
b a
b
a b X
Gnd X X
a b
Gnd

UNIT – I - Stick and Layout Diagrams

 LAYOUTS
The CMOS NOR Gate

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 LAYOUT
S
The 3-Input NAND
Gate
3-input NAND

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 LAYOUTS
The Transmission Gate

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 LAYOUTS
The 3-D View of a Design

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 LAYOUT
S
GENERAL LAYOUT GUIDELINES
1. The electrical gate design must be completed by checking
the followings:
a. Right power and ground supplies
b. Noise at the gate input
c. Faulty connections and transistors
d. Improper ratios
e. Incorrect clocking and charge sharing
2. VDD and the VSS lines run at the top and the bottom of the design
3. Vertical poysilicon for each gate input
4. Order polysilicon gate signals for maximal connection
between transistors
5. The connectivity requires to place NMOS close to VSS and PMOS
close to VDD
6. Connection to complete the logic must be made using poly, metal
and even metal2
UNIT – I - Stick and Layout Diagrams
 LAYOUT
S
GENERAL LAYOUT GUIDELINES
The factors for density improvement are (optimization):

• Efficient routing space usage. They can be placed over the cells or
even in multiple layers.

• Source drain connections must be merged better.

• White (blank) spaces must be minimum.

• The devices must be of optimum sizes.

• Transparent routing can be provided for cell to

cell interconnection, this reduces global wiring problems
UNIT – I - Stick and Layout Diagrams
 LAYOUT
S
LAYOUT OPTIMIZATION FOR PERFORMANCE
1. Vary the size of the transistor according to its position in series. The transistor
closest to the output is the smallest. The transistor nearest to the VSS line is the
largest. This helps in increasing the performance by 30%. A three input NAND
gate with the varying size is shown.

UNIT – I - Stick and Layout Diagrams

 LAYOUT
S
LAYOUT OPTIMIZATION FOR PERFORMANCE
1. When drains are connected in parallel, must try and reduce the number of
drains in parallel i.e. wherever possible must try and connect drains in series at
least at the output. This arrangement could reduce the capacitance at the output
enabling good voltage levels.

UNIT – I - Stick and Layout Diagrams

 BASIC PHYSICAL
DESIGN
The VLSI design flow for any IC design is as follows

1. Specification (problem
definition)

2. Schematic (gate level design) (equivalence

check)

3. Layout (equivalence
check)

4. Floor Planning

5. Routing, Placement
UNIT – I - Stick and Layout Diagrams
ANY Qs?