EECS 105 Fall 2003, Lecture 22

Lecture 22:
Multistage Amps

Prof. Niknejad

Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 22 Prof. A. Niknejad

Lecture Outline

 Finish Current Mirrors

 An Example Using Cascodes
 Multistage Amps
 Cascode Amplifier: Magic!

Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 22 Prof. A. Niknejad

The Integrated “Current Mirror”


M1 and M2 have the same
VGS
 If we neglect CLM (λ=0),
then the drain currents are
equal
 Since λ is small, the
High Res
currents will nearly mirror
Low Resis
one another even if Vout is
not equal to VGS1

We say that the current IREF
is mirrored into iOUT
 Notice that the mirror
works for small and large
signals!
Department of EECS University of California, Berkeley
EECS 105 Fall 2003, Lecture 22 Prof. A. Niknejad

Current Mirror as Current Source

 The output current of M2 is only weakly dependent on vOUT

due to high output resistance of FET
 M2 acts like a current source to the rest of the circuit
Department of EECS University of California, Berkeley
EECS 105 Fall 2003, Lecture 22 Prof. A. Niknejad

Small-Signal Resistance of I-Source

Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 22 Prof. A. Niknejad

Improved Current Sources

Goal: increase roc

Approach: look at amplifier output resistance
results … to see topologies that boost resistance

Rout  ro

Looks like the output

impedance of a common-
source amplifier with source
degeneration

Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 22 Prof. A. Niknejad

Effect of Source Degeneration

vt  (it  g m vgs )ro  vRS

vgs  vRS
vRS  it RS
1
Req  vt  (it  g m RS it )ro  it RS
gm
vt
Ro   1  g m RS  ro
it
 Equivalent resistance loading gate is dominated by
the diode resistance … assume this is a small
impedance
 Output impedance is boosted by factor 1  g m RS 

Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 22 Prof. A. Niknejad

Cascode (or Stacked) Current Source

Insight: VGS2 = constant AND

VDS2 = constant
Small-Signal Resistance roc:

Ro  1  g m RS  ro

Ro  1  g m ro  ro

Ro  g m r02  ro

Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 22 Prof. A. Niknejad

Drawback of Cascode I-Source

Minimum output voltage to keep both transistors in

saturation: V V V
OUT , MIN DS 4, MIN DS 2, MIN

VDS 2, MIN  VGS 2  VT 0  VDSAT 2

VD 4  VDSAT 2  VGS 4  VGS 2  VGS 4  VT 0
iOUT

vOUT
VOUT , MIN  VGS 2  VGS 4  VT 0
Department of EECS University of California, Berkeley
EECS 105 Fall 2003, Lecture 22 Prof. A. Niknejad

Current Sinks and Sources

Sink: output current goes Source: output current comes

to ground from voltage supply

Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 22 Prof. A. Niknejad

Current Mirrors
Idea: we only need one reference current to set up all the
current sources and sinks needed for a multistage amplifier.

Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 22 Prof. A. Niknejad

Multistage Amplifiers

Necessary to meet typical specifications for any of the 4 types

We have 2 flavors (NMOS, PMOS) of CS, CG, and CD and

the npn versions of CE, CB, and CC (for a BiCMOS
process)

What are the constraints?

1. Input/output resistance matching

1. DC coupling (no passive elements to block the signal)

Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 22 Prof. A. Niknejad

Summary of Cascaded Amplifiers

General goals:

1. Boost the gain parameter (except for buffers)

2. Optimize the input and output resistances

Rin Rout
Voltage:  0
Current: 0 
Transconductance:  
Transresistance: 0 0
Department of EECS University of California, Berkeley
EECS 105 Fall 2003, Lecture 22 Prof. A. Niknejad

Start: Two-Stage Voltage Amplifier

• Use two-port models to explore whether the combination

“works”

CE1 CE2

CE1,2

Results of new 2-port: Rin = Rin1, Rout = Rout2

Av  Gm1  Rin 2 || Rout1    Gm 2 Rout 2 

Av  Gm1Gm 2  Rin 2 || Rout1  Rout 2 

Department of EECS University of California, Berkeley
EECS 105 Fall 2003, Lecture 22 Prof. A. Niknejad

Add a Third Stage: CC

Goal: reduce the output resistance

(important spec. for a voltage amp)

CE1 CE2 CC3

Output resistance:
1 R 1 r || r
Rout   S   o 2 oc 2
g m3  g m3 

Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 22 Prof. A. Niknejad

Using CMOS Stages

CS1 CS2 CD3

Input resistance: 

Voltage gain (2-port parameter):

Av   g m1  ro1 || roc1   g m 2  ro 2 || roc 2 
Output resistance:
1
Rout 
g m  g mb
Department of EECS University of California, Berkeley
EECS 105 Fall 2003, Lecture 22 Prof. A. Niknejad

Multistage Current Buffers

Are two cascaded common-base stages better than

one?

CB1 CB2

Input resistance: Rin = Rin1

Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 22 Prof. A. Niknejad

Two-Port Models

Rout  Rout 2  r02 1  g m 2 r 2 || RS 2  || roc 2

Output impedance of stage #1 (large)

Rout  r02  g m 2 r 2  || roc 2    o ro 2  || roc 2

Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 22 Prof. A. Niknejad

Common-Gate 2nd Stage

Rout  Rout 2  r02 1  g m 2 RS 2  || roc 2

Rout  Rout 2  r02 1  g m 2 ro1 || roc1  || roc 2

Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 22 Prof. A. Niknejad

Second Design Issue: DC Coupling

Constraint: large inductors and capacitors are not
available
Output of one stage is directly connected to the
input of the next stage  must consider DC
levels … why?

3.2V

Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 22 Prof. A. Niknejad

Alternative CG-CC Cascade

Use a PMOS CD Stage: DC level shifts upward

3.2V

Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 22 Prof. A. Niknejad

CG Cascade: DC Biasing

Two stages can have different supply currents

Extreme case:
IBIAS2 = 0 A

Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 22 Prof. A. Niknejad

CG Cascade: Sharing a Supply

First stage has no current

supply of its own  its output
resistance is modified

Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 22 Prof. A. Niknejad

The Cascode Configuration

Common source / common gate

cascade is one version of a cascode
(all have shared supplies)

DC bias:

Two-port model: first stage

has no current supply of its own

Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 22 Prof. A. Niknejad

Cascode Two-Port Model

CS1* CG2

Output resistance of first stage = Rout ,CS *  R down ,CS  ro1

Rout roc 2 || (1  g m ro1 )ro 2

Gm  g m1

Rin  

Why is the cascode such an important configuration?

Department of EECS University of California, Berkeley
EECS 105 Fall 2003, Lecture 22 Prof. A. Niknejad

Miller Capacitance of Input Stage

Find the Miller capacitance for Cgd1

Input resistance to
common-gate
second stage is low 
gain across
Cgd1 is small.

Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 22 Prof. A. Niknejad

Two-Port Model with Capacitors

Miller capacitance: C M  (1  AvC gd 1 )C gd 1

1 g m1
AvCgd 1   g m1 ( || ro1 )    1
gm2 gm2

CM  2C gd 1
Department of EECS University of California, Berkeley
EECS 105 Fall 2003, Lecture 22 Prof. A. Niknejad

Generating Multiple DC Voltages

Stack-up diode-connected
MOSFETs or BJTs and
run a reference current
through them  pick off
voltages from gates or
bases as references

Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 22 Prof. A. Niknejad

Multistage Amplifier Design Examples

Start with basic two-stage transconductance

amplifier:

Why do this combination?

Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 22 Prof. A. Niknejad

Two-Stage Amplifier Topology

Direct DC connection: use NMOS then PMOS

Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 22 Prof. A. Niknejad

Current Supply Design

Assume that the reference is a

“sink” set by a resistor

Must mirror the reference

current and generate a sink for
iSUP 2

Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 22 Prof. A. Niknejad

Use Basic Current Supplies

Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 22 Prof. A. Niknejad

Complete Amplifier Topology

What’s missing? The device dimensions and the bias

voltage and reference resistor
Department of EECS University of California, Berkeley