UNIT-1

Digital computer: functional units

and their interconnections
• Computer Architecture:
Computer Architecture is a functional description
of requirements and design implementation for
the various parts of computer.It deals with
functional behavior of computer system. It comes
before the computer organization while
designing a computer.
2
• Computer Organization:
Computer Organization comes after the decide of
Computer Architecture first. Computer
Organization is how operational attribute are
linked together and contribute to realise the
architectural specification. Computer
Organization deals with structural relationship.
3
• Computer Organization: • Computer Architecture:
Computer Organization Computer Architecture is a
functional description of
comes after the decide of requirements and design
Computer Architecture first. implementation for the
Computer Organization is various parts of
how operational attribute computer.It deals with
functional behavior of
are linked together and computer system. It comes
contribute to realise the before the computer
architectural specification. organization while
Computer Organization designing a computer
deals with structural
relationship.

4
 It is a processing machine that process the information in
digital form i.e. (0’s & 1’s).
 Means digital computer can only understand binary language

(0’s & 1’s).

 If any analog quantity is to be processed, they must be

converted into digital form before processing

 Functions performed by a computer are:

◦ Accepting information to be processed as input.

◦ Storing a list of instructions to process the information.
◦ Processing the information according to the list of instructions.
◦ Providing the results of the processing as output.
 What are the functional units of a computer?
 The block diagram of a digital computer is shown below.
Whatever may be the type, size and capacity of the computer,
it should have these five blocks.

Input Processing Output

 Input Storage Output Unit
Devices

Control Unit

ALU
 The computer consists of four main parts. These are as
follows:
(i) Central processing unit.
(ii) Memory
(iii) Input Devices
(iv) Output devices
 Central Processing Unit
The CPU is the place where computations are performed. It is the brain and heart
of a computer.
 CPU interprets instruction and process data contained in computer program.
 CPU has two component

1. ALU ( Arithmetic & Logic Unit)

2. CU ( Control Unit )
The arithmetic logic unit (ALU) of the CPU performs the typical arithmetic operations
such as addition, subtraction, multiplication, and division. Computers use the
binary number system, to represent numbers. The binary number system has only
two digits 0 and 1.

Control Unit control all the operation in computer. It is the controller of the system.
 It also control all the devices connected to CPU.
 It also control the flow of data from i/p devices to memory and memory to o/p
devices.
 Memory: Memory is the location where data and programs are
stored while being processed by the CPU. Memory is the main
storage unit in a computer.
 Memory consists of primary (main) memory and secondary

memory. The data stored in main memory (RAM) is volatile

and is erased as soon as the power supply is cut off.
Therefore, secondary memory is used to store data. In
secondary memory (diskettes) data is stored permanently.
 Input Devices: Input is the process of entering and translating
incoming data into machine readable form.
 Any hardware item which attached to the main unit of a

computer that houses the CPU is referred to as peripheral

device.
 An input device is a peripheral device through which data are

entered and transformed into machine readable form. Input

devices are mainly used to communicate information between
humans and computer. Example: Keyboard, mouse etc.
 Output Devices: An output device is a peripheral device that
allows a computer to communicate information to humans or
another machine by accepting data from the computer and
transforming them into a usable form. The output devices
gives the desired result to the user. Example: Monitor, Printer
etc.
• For a computer to achieve its operation, the functional units need to
communicate with each other.
• In order to communicate, they need to be connected.

Input Output Memory Processor

Bus

• Functional units may be connected by a group of parallel wires.

• The group of parallel wires is called a bus.
• Each wire in a bus can transfer one bit of information.
• The number of parallel wires in a bus is equal to the word length of
a computer

13
 A group of wires connecting two or more devices and
providing a path to perform communication is called bus.
 A bus that connect major computer component such as

( CPU , Memory , I/O) is called system bus.

 A bus is a set of physical connections (cables, printed circuits,
etc.) which can be shared by multiple hardware components
in order to communicate with one another.

 The purpose of buses is to reduce the number of "pathways"

needed for communication between the components, by
carrying out all communications over a single data channel.
This is why the metaphor of a "data highway" is sometimes
used.
 Control Lines
Data Lines

•Control lines:
– Signal requests and acknowledgments
– Indicate what type of information is on the data lines
•Data lines carry information between the source

and the destination:

– Data and Addresses
– Complex commands
•A bus transaction includes two parts:
– Sending the address
– Receiving or sending the data
 Master send address
Bus Bus
Master Data can go either way Slave

• A bus transaction includes two parts:

– Sending the address
– Receiving or sending the data
• Master is the one who starts the bus transaction by:
– Sending the address
• Salve is the one who responds to the address by:
– Sending data to the master if the master ask for data
– Receiving data from the master if the master wants to send
data
• Output is defined as the Processor sending data to the I/O
device:
Step 1: Request Memory
Control (Memory Read Request)
Processor Data (Memory Address) Memory

I/O Device (Disk)

Step 2: Read Memory

Control
Processor Data Memory

I/O Device (Disk)

Step 3: Send Data to I/O Device

Control (Device Write Request)
Processor Data Memory
(I/O Device Address
I/O Device (Disk) and then Data)
 ° Input is defined as the Processor receiving data from the I/O
device:

Step 1: Request Memory

Control (Memory Write Request)
Processor Data (Memory Address) Memory

I/O Device (Disk)

Step 2: Receive Data

Control (I/O Read Request)
Processor Data Memory
(I/O Device Address
I/O Device (Disk) and then Data)
 A bus is characterised by the amount of information that can
be transmitted at once. This amount, expressed in bits,
corresponds to the number of physical lines over which data
is sent simultaneously.
 A 32-wire ribbon cable can transmit 32 bits in parallel. The
term "width" is used to refer to the number of bits that a bus
can transmit at once.
 Additionally, the bus speed is also defined by its frequency
(expressed in Hertz), the number of data packets sent or
received per second. Each time that data is sent or received
is called a cycle.
 This way, it is possible to find the maximum transfer speed of
the bus, the amount of data which it can transport per unit of
time, by multiplying its width by its frequency. A bus with a
width of 16 bits and a frequency of 133 MHz, therefore, has a
transfer speed equal to:
 16 * 133 *106 = 2128*106 bit/s,
 or 2128*106/8 = 266*106 bytes/s
 or 266*106 /1000 = 266*103 KB/s
 or 266*103 /1000 = 266 MB/s
• Processor-Memory Bus (design specific)
– Short and high speed
– Only need to match the memory system
• Maximize memory-to-processor bandwidth
– Connects directly to the processor
• I/O Bus (industry standard)
– Usually is lengthy and slower
– Need to match a wide range of I/O devices
– Connects to the processor-memory bus or backplane bus
• Backplane Bus (industry standard)
– Backplane: an interconnection structure within the chassis
– Allow processors, memory, and I/O devices to coexist
– Cost advantage: one single bus for all components
 Backplane Bus
Processor Memory

I/O Devices

• A single bus (the backplane bus) is used for:

– Processor to memory communication
– Communication between I/O devices and memory
• Advantages: Simple and low cost
• Disadvantages: slow and the bus can become a major
bottleneck
• Example: IBM PC
 Processor Memory Bus
Processor Memory

Bus Bus Bus

Adaptor Adaptor Adaptor

I/O I/O I/O

Bus Bus Bus

• I/O buses tap into the processor-memory bus via bus

adaptors:
– Processor-memory bus: mainly for processor-memory traffic
– I/O buses: provide expansion slots for I/O devices
• Apple Macintosh-II
– NuBus: Processor, memory, and a few selected I/O devices
– SCCI Bus: the rest of the I/O devices
 Processor Memory Bus
Processor Memory

Bus
Adaptor
Bus
Adaptor I/O Bus
Backplane Bus
Bus I/O Bus
Adaptor

• A small number of backplane buses tap into the processor-memory

bus
– Processor-memory bus is used for processor memory traffic
– I/O buses are connected to the backplane bus
• Advantage: loading on the processor bus is greatly reduced
• Synchronous Bus:
– Includes a clock in the control lines
– A fixed protocol for communication that is relative to the
clock
– Advantage: involves very little logic and can run very fast
– Disadvantages:
• Every device on the bus must run at the same clock rate
• To avoid clock skew, they cannot be long if they are fast
• Asynchronous Bus:
– It is not clocked
– It can accommodate a wide range of devices
– It can be lengthened without worrying about clock skew
– It requires a handshaking protocol
There are three main bus groups or System bus can be
separated into three functional group

 ADDRESS BUS

 DATA BUS

 CONTROL BUS
• The Data Bus carries the data which is transferred
throughout the system.

Data Bus
• It is bi-directional.

• Examples of data transfers

– Program instructions being read from memory into
MPU(Memory Protection Unit).
– Data being sent from MPU to I/O port
– Data being read from I/O port going to MPU
– Results from MPU sent to Memory
• These are called read and write operations
• An address is a binary number that identifies a
specific memory storage location or I/O port
involved in a data transfer

• The Address Bus is used to transmit the address

of the location to the memory or the I/O port.
Address Bus

• The Address Bus is unidirectional (one way):

addresses are always issued by the MPU.
• The Control Bus: is another group of signals whose
functions are to provide synchronization (timing
control) between the MPU and the other system
components.

• Control signals are unidirectional, and are mainly

outputs from the MPU.
Control Bus
• Example Control signals
– RD: read signal asserted to read data into MPU
– WR: write signal asserted to write data from MPU
 Bus arbitration scheme:
◦ A bus master wanting to use the bus asserts the bus request
◦ A bus master cannot use the bus until its request is granted
◦ A bus master must signal to the arbiter after finish using the bus
 Bus arbitration schemes usually try to balance two factors:
◦ Bus priority: the highest priority device should be serviced first
◦ Fairness: Even the lowest priority device should never be completely
locked out from the bus
 A device that initiates data transfers on the bus at any given
time is called a bus master.
 In a computer system, there may be more than one bus

master such as a DMA controller or a processor etc.

 These devices share the system bus and when a current

master bus relinquishes another bus can acquire the control

of the processor.
 Bus arbitration is a process by which next device becomes the

bus controller by transferring bus mastership to another bus.

 There are two types of bus arbitration namely
◦ Centralized Arbitration.
◦ Distributed Arbitration.
 In centralized bus arbitration, a single bus arbiter performs
the required arbitration. The bus arbiter may be the processor
or a separate controller connected to the bus.
 There are three different arbitration schemes that use the

centralized bus arbitration approach. There schemes are:

 a. Daisy chaining
 b. Polling method
 c. Independent request
 It is simple and cheaper method. All masters make use of the
same line for bus request.
 In response to the bus request the controller sends a bus
grant if the bus is free.
 The bus grant signal serially propagates through each master
until it encounters the first one that is requesting access to
the bus. This master blocks the propagation of the bus grant
signal, activities the busy line and gains control of the bus.
 Therefore any other requesting module will not receive the
grant signal and hence cannot get the bus access.
 Advantages:
◦ Simplicity and Scalability.
◦ The user can add more devices anywhere along the chain, up to a
certain maximum value.
 Disadvantages:
◦ The value of priority assigned to a device depends on the position of
the master bus.
◦ Propagation delay arises in this method.
◦ If one device fails then the entire system will stop working.
 In this the controller is used to generate the addresses for the master.
Number of address line required depends on the number of master
connected in the system.
 For example, if there are 8 masters connected in the system, at least
three address lines are required.
 In response to the bus request controller generates a sequence of
master address. When the requesting master recognizes its address, it
activated the busy line ad begins to use the bus.
 Advantages –
◦ This method does not favor any particular device and processor.
◦ The method is also quite simple.
◦ If one device fails then the entire system will not stop working.

 Disadvantages –
◦ Adding bus masters is difficult as increases the number of address
lines of the circuit.
 The figure below shows the system connections for the independent request
scheme.
 In this scheme each master has a separate pair of bus request and bus grant lines
and each pair has a priority assigned to it.
 The built in priority decoder within the controller selects the highest priority
request and asserts the corresponding bus grant signal.
 Advantages –
◦ This method generates a fast response.
◦ Speed is independent of number of devices connected.
 Disadvantages –
◦ Hardware cost is high as a large no. of control lines is required.
◦ No. of control lines required is more therefore connecting large
number of bus masters is difficult.
 In distributed arbitration, all devices participate in the
selection of the next bus master.
 In this scheme each device on the bus is assigned a4-bit

identification number.
 The number of devices connected on the bus when one or

more devices request for the control of bus, they assert the
start-arbitration signal and place their 4-bit ID numbers on
arbitration lines, ARB0 through ARB3.
Here, all the devices participate in the selection of the
next bus master.
Each device on the bus is assigned a 4 bit
identification number.
When one or more devices request control of the bus,
they assert the start arbitration signal and place their
4-bit identification numbers on arbitration lines
through ARB3.
Each device compares the code and changes its bit
position accordingly.
It does so by placing a 0 at the input of their drive.
The distributed arbitration is highly reliable because
the bus operations are not dependant on devices.
 Digital System: An interconnection of hardware modules
that do a certain task on the information.
 Registers + Operations performed on the data stored in

them = Digital Module

 Modules are interconnected with common data and control

paths to form a digital computer system

 Register is a very fast computer memory, used to store
data/instruction in-execution.
 A Register is a group of flip-flops .
 In electronics, a flip-flop or latch is a circuit that has two
stable states and can be used to store state information – a
bistable multivibrator.
 The circuit can be made to change state by signals applied to

one or more control inputs and will have one or two outputs
 Microoperations: is an elementry operations
executed on data stored in one or more
registers.
 For any function of the computer, a sequence
of microoperations is used to describe it
 The result of the operation may be:
◦ replace the previous binary information of a
register or transferred to another register
◦ Examples of microoperations are shift,
count, clear and load.
Shift Right Operation
1011011100 1101110010
10
 The internal hardware organization of a
digital computer is defined by specifying:
 The set of registers it contains and their function
 The sequence of microoperations performed on the
binary information stored in the registers
 The control that initiates the sequence of
microoperations
 Registers + Microoperations Hardware +
Control Functions = Digital Computer
 Register Transfer Language (RTL) : a symbolic notation to
describe the microoperation transfers among registers
Next steps:
◦ Define symbols for various types of microoperations,
◦ Describe the hardware that implements these microoperations
 Computer registers are designated by capital letters
(sometimes followed by numerals) to denote the function of
the register
 R1: processor register
 MAR: Memory Address Register (holds an address for a memory unit)
 PC: Program Counter
 IR: Instruction Register
 SR: Status Register
 The most common way to represent a register ,is by
rectangle box with name of register inside
 The individual flip-flops in an n-bit register are numbered

in sequence from 0 to n-1 (from the right position toward

the left position)
 4

REGISTER TRANSFER
Designation of a register - a register
- portion of a register
- a bit of a register
Common ways of drawing the block diagram of a register
Register Showing individual bits
R1 7 6 5 4 3 2 1 0

15 0 15 87 0
R2 PC (H) PC(L)
Numbering of bits Subfields

Representation of a
transfer(parallel) R2  R1
A simultaneous transfer of all bits from the
source to the destination register, during one clock pulse
Representation of a controlled(conditional) transfer P:
R2  R1
A binary condition(p=1) which determines when the transfer
is to occur
If (p=1) then (R2  R1)
 Information transfer from one register to another is
described by a replacement operator: R2 ← R1
 This statement denotes a transfer of the content of
register R1 into register R2
 The transfer happens in one clock cycle
 The content of the R1 (source) does not change
 The content of the R2 (destination) will be lost and
replaced by the new data transferred from R1
 We are assuming that the circuits are available from
the outputs of the source register to the inputs of
the destination register, and that the destination
register has a parallel load capability
 Conditional transfer occurs only under a
control condition

 Representation of a (conditional) transfer

P: R2 ← R1
 A binary condition (P equals to 0 or 1)
determines when the transfer occurs
 The content of R1 is transferred into R2 only
if P is 1
 Implementation of controlled transfer
P: R2  R1
Block diagram Control P Load
R2 Clock
Circuit
n
R1

Timing diagram t t+1

Clock

Load
Transfer occurs here

Basic Symbols for Register Transfers

Symbols Description Meaning
Capital letters Denotes a register MAR, R2
and numerals
Parentheses ( ) Denotes a part of a register R2(0-7), R2(L)
Arrow  Denotes transfer of information R2  R1
Colon : Denotes termination of control function P:
Comma , Separates two micro-operations A  B, B  A

06/09/24
 Unconditional
R1 ← R2
 Conditional
P: R1 ← R2
 Simultaneous
R1 ← R2 , R3 ← R2
 If two or more operations are to
occur simultaneously, they are
separated with commas

P: R3  R5 ,, MAR  IR

 Here, if the control function P = 1,

load the contents of R5 into R3,
and at the same time (clock), load
the contents of register IR into
register MAR
 Basic Symbols for Register Transfers
Symbol Description Examples
Letters & Denotes a register MAR, R2
numerals
Parenthesis ( ) Denotes a part of a R2(0-7), R2(L)
register
Arrow ← Denotes transfer of R2 ← R1
information
Comma , Separates two R2 ← R1, R1 ←
microoperations R2
Every statement written in a register transfer notation implies a
H/W construction for implementing the transfer.

The internal H/W organization of a digital computer is best

defined by specifying :

1.The set of register it contains.

2.Sequence of micro-operation performed on the binary

information stored in the register.

3.The control that initiates the sequence of micro-operation.

 A MULTIPLEXER is a digital circuit that has multiple inputs
and a single output.
 The selection of one of the n inputs is done by the select
inputs .
 It has one output selected at a time.
 It is also known as DATA SELECTOR.
 A multiplexer has

1. N data inputs(multiple)
2. 1 output (single) 
3. M select inputs, with 2M =N
 2-to-1 (1 select line)
 4-to-1 (2 select lines)
 8-to-1 (3 select lines)
 16-to-1 (4 select lines)
 8:1 MUX has 8 inputs(D0, D1, D2, D3, D4, D5, D6, D7) & 3
 select lines(S0,S1, S2,)
 A shared communication path consisting of one or more
connection lines is known as bus
 Bus transfer : The transfer of data through bus is known as

bus transfer.
 Memory Transfer : When a data is read from memory or is

stored in memory is referred to as memory transfer.

 Paths must be provided to transfer
information from one register to another
 A Common Bus System is a scheme for
transferring information between registers
in a multiple-register configuration
 A bus: set of common lines, one for each bit
of a register, through which binary
information is transferred one at a time
 Control signals determine which register is
selected by the bus during each particular
register transfer
 One way of constructing a common bus system is with
multiplexer:
 The multiplexer select the source register whose binary

information is then placed on the bus.

 For k register of n bits, each produce an n– line common
bus.
 The number of multiplexer needed is equal to n( no of bits in

each register) The size of each multiplexer must be k ×1

 A digital computer has a common bus system for 16 registers of 32 bits each.The bus is
constructed with multiplexers.
a) How many selection inputs are there in each multiplier?

b) What sizes of multiplexers are needed.

c) How many multiplexers are there in the bus?

 Ans-The following data is given. 16 registers of 32 bits universal bus systema)

a) How many selection inputs are there in each multiplier?

Ans:-The bus is constructed with multiplexers.Therefore we have a universal bus system of 32
line. 16 registers are equal to 2*4 registers therefore 4 selection inputs are there in each
multiplier.
b)What are the sizes of multiplexers needed?
ANS:- sizes of multiplexers are needed are a 32X1 multiplexer
c)How many multiplexers are there in the bus?
Ans:- On the bus, there are 16 multiplexers
1. Accepts a value and decodes it
◦ Output corresponds to value of n inputs
 2. A decoder consists of:
 Inputs (n)
 Outputs (2 n , numbered from 0 -2 n - 1)
 Selectors / Enable (active high or active low)
 The decoder has the characteristic that for each
of the possible 2 𝑛 binary input numbers which
can be taken by the n input cells, the matrix will
have a unique one of its 2 𝑛 output lines selected.
 This simple example above of a 2-to-4 line
binary decoder consists of an array of four AND gates.
 The 2 binary inputs labelled A and B are decoded into one

of 4 outputs, hence the description of 2-to-4 binary decoder.

 Each output represents one of the miniterms of the 2 input

variables, (each output = a miniterm).

A2 A1 A0 D0 D1 D2 D3 D4 D5 D6 D7

0 0 0 1
0 0 1 1
0 1 0 1

0 1 1 1

1 0 0 1

1 0 1 1
1 1 0 1

1 1 1 1
 The transfer of information from a bus into
one of many destination registers is done:
◦ By connecting the bus lines to the inputs of all
destination registers and then:
◦ activating the load control of the particular
destination register selected
We write: R2 ← C to symbolize that the
content of register C is loaded into the
register R2 using the common system bus
 It is equivalent to: BUS ←C, (select C)

R2 ←BUS (Load R2)

 A bus system can be constructed with three-state buffer gates
instead of multiplexers
 A three-state buffer is a digital circuit that exhibits three

states: logic-0, logic-1, and high-impedance (Hi-Z)

Control input C

Normal input A Output B

Three-State Buffer
 C=1

Buffer
A B A B

C=0

Open Circuit
A B A B
 Bus lines

Load
Reg. R0 Reg. R1 Reg. R2 Reg. R3

D 0 D1 D2 D 3
z E (enable)
Select 2x4
w
Decoder

Three-State Bus Buffers

Normal input A Output Y=A if C=1
High-impedence if C=0
Control input C

Bus line with three-state buffers

Bus line for bit 0
A0
B0
C0
D0

S0 0
Select 1
S1 2
Enable 3
 S1 0
Select
S0 1
Bus line for bit 0
2×4 A0
Decoder 2
Enable E
3

B0

C0

Bus line with three-state

buffer (replaces MUX0 in the D0
previous diagram)
 A0 A1

2X4 B0 B1
DECODER

C0 C1

D0 D1

Output for 0 Output for bit 1

bit
 Memory read : Transfer from memory
 Memory write : Transfer to memory
 Data being read or wrote is called a memory

word (called M)- (refer to section 2-7)

 It is necessary to specify the address of M

when writing /reading memory

 This is done by enclosing the address in

square brackets following the letter M

 Example: M[0016] : the memory contents at

address 0x0016
 Assume that the address of a memory unit is stored in a
register called the Address Register AR
 Lets represent a Data Register with DR, then:
 Read: DR ← M[AR]
 Write: M[AR] ← DR
 AR
x0C 19
x12 x0E 34
R1 x10 45
100 x12 66
x14 0
x16 13
R1←M[AR] x18 22

RAM

R1 R1
100 66