Tessent™: Scan and ATPG

Module 1

Basic Concepts
 Objectives

Upon completion of this module, you should be able to:

 Describe the basic Design-for-Test (DFT) technology.

 Explain the DFT design flow.
 Invoke ATPG tools in non-gui mode.
 Use commands to access online help and documentation.

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 Types of Test
 Functional tests
 Verify circuit functionality
– Simulation, verification of design logic
– Analog, digital, and mixed-signal testing
 Can be board, subsystem, system, prototype, etc.
– Includes pin parametrics
– Placing part into “test mode”
 Structural tests
 Target manufacturing defects
 Consists of:
– Scan
– AC Scan
– Logic BIST
– Memory BIST
– Iddq

1-3 • Tessent: Scan and ATPG: Basic Concepts Copyright © 1999-2009 Mentor Graphics Corporation
 Why Design-for-Test?

 Increased Productivity:
 Shorter time-to-market
 Reduced design cycle
 Measurable and predictable results
 Detailed circuit knowledge not necessary

 Improved Quality:
 Reduced Defects per Million (DPM) shipped products
 Improved quality of test

1-4 • Tessent: Scan and ATPG: Basic Concepts Copyright © 1999-2009 Mentor Graphics Corporation
 Testing and Cost
 Low number of defective parts (DPM) is critical
 Cost of repair grows exponentially throughout design cycle
 Cost of bad part in critical device (for example, a pacemaker
or airplane) is immeasurable

1000x

100x
Cost

10x

1x

Analysis Design Test Field

1-5 • Tessent: Scan and ATPG: Basic Concepts Copyright © 1999-2009 Mentor Graphics Corporation
 What Is Testability?
 Controllability and Observability
 Ability to put a design into a known initial state, and then control and
observe internal signal values

 Circuit with DFFs:

 Low testability

1-6 • Tessent: Scan and ATPG: Basic Concepts Copyright © 1999-2009 Mentor Graphics Corporation
 What Is Testability? (Cont.)
 A highly testable design:
 A circuit that can be placed into a known initial state.
 PIs are controllable.
 POs are observable and measurable.
 DFFs replaced with MUX scan:
 A highly testable design.

1-7 • Tessent: Scan and ATPG: Basic Concepts Copyright © 1999-2009 Mentor Graphics Corporation
 Stuck-At Fault Model
 Industry standard pattern
set.
 Fault models are logic
targets for defects.
 A fault is detected:
 When a difference is
observed between a “good”
and “faulty” circuit.
 Most common fault model:
 Most defects are detected with
the stuck-at fault model.
 A terminal of a gate is
permanently stuck-at 0 or 1.
 Detects:
– Opens
– Shorts
– Bridging faults
– Others…

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 Fault Models
 Fault models:
 Stuck-at-fault Covered faults All other
faults
 Transition fault
Transition
 Path delay
 IDDQ
 Open
 Timing aware
 Bridge fault
– Two models exist:
• Layout aware test based on
Stuck-at
physical attributes
• Statistical model testing
each gate terminal multiple
times (multiple detection
model)

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 At-Speed Fault Models: Transition and Path Delay
Transition fault model

 Used in more than half of products in industry

 Delay fault model:
 Slow-to-rise node
 Slow-to-fall node
 Application of two cycles:
 Launch
 Capture
 Detects:
 Partially conducting transistors
 Resistive bridge defects

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 At-Speed Fault Models: Transition and Path Delay (Cont.)
Path delay

 Limited use—speed binning and silicon trends

 Path delay fault model:
 Slow-to-rise path
 Slow-to-fall path
 Application of two cycles:
 Launch
 Capture
 Tests for lumped time delay:
 Sum of time delays that stack up
 Paths from static timing analysis through a specific path
 Detects:
 Partially conducting transistors
 Diffusions

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 IDDQ Fault Model
 Limited use—many chips too noisy for iddq
 Measures quiescent power supply current during the stable state
 Takes time, but attains 80-90% test coverage
 Detects:
CMOS transistor stuck-on/some stuck-open conditions
 Bridging faults

 Partially conducting transistors

VDD
0
A 1/ 0 P1
0/1
B Y 0
A P2
Y
0 1/0
B N2

Faulty transistor stuck “on” N1 VSS

1-12 • Tessent: Scan and ATPG: Basic Concepts Copyright © 1999-2009 Mentor Graphics Corporation
 Layout-Aware Bridge Fault Model
 Limited use—mostly for very high quality requirements.
 Standardized at some companies.
 Deterministic bridge ATPG.
 Layout-aware test targets faults based on physical attributes.

Calibre GDSII
Potential
Potential Bridging
Bridging Faultlist
Faultlist Extraction
Extraction
Rules

Bridged node list

Tessent TestKompress
Netlist
Deterministic
Deterministic Bridging
Bridging ATPG
ATPG

SET FAult Type Bridge

LOAd FAult Sites
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 Bridge Fault: Defect-Aware —Test Multiple Detection
 Standardized at some companies.
 Every fault is detected “n” times through different control and
observe paths.
 ATPG randomly targets each stuck-at or transition fault.
 Each detection increases the statistical chance of detecting a bridge.
 Embedded Multiple Detect (EMD) is the standard usage model.
 Increases test quality without adding additional patterns.
0
1
Pattern 1 Pattern 2 0 0
0 0
Control 010
011
Fault-Free 01 1
00 1
Stuck-at-1 11
01
Bridge 01 0 1
01 1 1

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 Scan Design
 Internal scan is a structured DFT technique that
 Replaces sequential storage elements with scan cells
 Stitches scan cells into a serial scan register (scan chain)
 Makes sequential circuitry appear combinational
 Structural test technique
 Tests pieces instead of entire function

1-15 • Tessent: Scan and ATPG: Basic Concepts Copyright © 1999-2009 Mentor Graphics Corporation
 Scan Cell Types
 Scan cell types:
 Mux DFF
 Level-Sensitive Scan Design (LSSD)
 Clocked Scan

1-16 • Tessent: Scan and ATPG: Basic Concepts Copyright © 1999-2009 Mentor Graphics Corporation
 Mux DFF Scan Cell
 Used in most designs
 Multiplexer selects data input:
 D in normal mode
 Scan_in (SI) scan mode
 Scan_enable (SE) selects mode of operation
 Increased propagation delay
 Adds 5-15% area overhead
 Standard approach today Replaced by
MUX-D Scan Cell
Original
Flip-Flop
D N_2 DFF 1

D Q
SI D scan_out
MUX 1
SE DFF
CLK
CLK

1-17 • Tessent: Scan and ATPG: Basic Concepts Copyright © 1999-2009 Mentor Graphics Corporation
 LSSD Scan Cell
 Sometimes used in high speed
designs such as processors. Original Latch
 Level-sensitive scan design
modes of operation: D Q
Latch 1
 Normal mode CLK
– Master latch captures system
data D using the system (CLK)
and outputs L1.
 Test mode
Replaced by LSSD Scan Cell
– Two non-overlapping clocks
(ENSA and ENSB) shift data D Q
through the latches. SI Master
– Scan output is SO. CLK Latch
Slave SO
ENSA
Latch
ENSB

1-18 • Tessent: Scan and ATPG: Basic Concepts Copyright © 1999-2009 Mentor Graphics Corporation
 Scan Chains
 Scan _Enable (SE):
 When active allows scan data to enter the registers.
 Scan input port (SI):
 Data is loaded into scan cells.
 Scan output port (SO):
 Data is read by shifting data out.

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 Scan Based Designs
 Normal mode (SE = 0):
 Sequential elements perform regular system functions.

1-20 • Tessent: Scan and ATPG: Basic Concepts Copyright © 1999-2009 Mentor Graphics Corporation
 Scan Based Designs (Cont.)
 Scan mode (SE = 1):
 Sequential elements are connected into one or more
shift registers (scan chains).
 Circuit appears combinational.

1-21 • Tessent: Scan and ATPG: Basic Concepts Copyright © 1999-2009 Mentor Graphics Corporation
 DFT Design Flow

Gate Level Insert

Netlist Scan

Insert
Scan Inserted
compression
Netlist
logic
Tessent TestKompress

Generate
Compression Logic
test patterns
Inserted Netlist
Tessent TestKompress

Test IC
Test
Patterns ATE

1-22 • Tessent: Scan and ATPG: Basic Concepts Copyright © 1999-2009 Mentor Graphics Corporation
 ATPG Flow

Gate-Level Netlist Design Rule Flattened Netlist

Checking
( DRC)

ATPG Libraries Fault List

Generate
Patterns Simulation
Dofiles
Testbench

Test Procedure Write Out Pattern Files

Files Patterns

 Existing fault lists and

Save Flattened pattern files can be
Netlist for read in.
Diagnostics  Test patterns written
out in WGL, STIL, other
file formats.
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 Insert Scan and Test Logic
Design
Requirements
 Insert full/partial scan
RTL Coding
 Perform testability analysis
RTL Design

 Check design rules (DRC) Synthesis

DRC Gate Level

 Synthesize test logic Scan Insertion Netlist

ATPG DRC Scan Inserted

Netlist
Tessent FastScan or
Tessent TestKompress

Test
Patterns
ATE

1-24 • Tessent: Scan and ATPG: Basic Concepts Copyright © 1999-2009 Mentor Graphics Corporation
 ATPG
Design
 Check design rules (DRC) Requirements

RTL Coding
 Generate test patterns for
production test
RTL Design
Synthesis

 Best for full-scan designs

DRC Gate Level
Scan Insertion Netlist
 Produce high test coverage

ATPG DRC Scan Inserted

 Generate compact pattern sets Tessent FastScan or
Netlist
Tessent TestKompress

Test
Patterns
ATE

1-25 • Tessent: Scan and ATPG: Basic Concepts Copyright © 1999-2009 Mentor Graphics Corporation
 Tessent TestKompress
Design
 Generates test patterns for Requirements

production
RTL Coding

 Compresses up to 100X test

RTL Design
time and data Synthesis

 Accommodates RTL or Scan Insertion

DRC Gate Level
Netlist
gate-level designs

 Increases test coverage EDT DRC Scan Inserted

Netlist
 Automatically masks X states Tessent TestKompress
necessary for effective at-
speed test Test
Patterns
ATE

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 ATPG Accelerator

 Reduces runtime by distributing Distributed ATPG

ATPG to multiple processors.
20
 Tool and slave processes can be 18

Absolute speed Up
16
run on one machine or on 14
12
multiple remote machines. 10
8
 Runs on all platforms DFT 6
4
software supports. 2
0
 No special licensing needed. 0 1 2 4 8 16 32 64
# of Slave Processes
 One license is used for four
processors.

For more information, refer to the Scan and ATPG Process Guide.

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 ATPG Accelerator Requirements
 Network job scheduling capability
 Load Sharing Function (LSF)
 Sun Grid Engine (SGE)
 Custom Job Scheduling

 Manual specification (does not require a job scheduler)

 Manual host must be able to create processes on slave host via
rsh or ssh.

 ATPG Accelerator variables

 Use the set distributed command to setup job scheduling.
 Use the add processors command to define host machines slave
processors.

 All processes must run the same version of the tool

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 Timing-Aware ATPG

 ATPG guided with timing information.

 Goal — at-speed test along long paths to detect small delay
defects.
 Use SDF (Standard Delay Format) information to select fault
excitation and propagation paths.
Weight selection of fault
Justify excitation condition propagation path on sum of delays
through largest possible delays downstream
upstream
A (Tr, Tf)
a (Tr, Tf)
B (Tr, Tf)

C (Tr, Tf)

b (Tr, Tf) D (Tr, Tf)

1-29 • Tessent: Scan and ATPG: Basic Concepts Copyright © 1999-2009 Mentor Graphics Corporation
 Timing-Aware ATPG (Cont.)
 Targets all gate terminals using an SDF file.
 Goes beyond stuck-at and transition fault models.
 Generates patterns that detect transition faults using timing
information in the SDF file.
 Uses the longest local detection path.
 Can be the biggest impact to reduce DPM (Defects Per
Million).
 Shown to have up to 50% reduction in DPM.
 Less effective if all paths are balanced (sometimes done for
power reasons.)
 Uses commands read sdf and set atpg timing.
 Fully documented usage and flow in the Timing-Aware ATPG
manual.

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 Basic TCL Scripting

 Basic TCL scripting is supported in Tessent FastScan,

Tessent TestKompress®, Tessent DFTAdvisor (hereafter
known as DFTAdvisor ) and Tessent Diagnosis.
 Use -tcl at invocation to access the TCL interface.
 Useful for reading in large pattern sets.

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Accessing UNIX Commands From the DFT Command Line

 To run UNIX/Linux operating system commands

within the DFT session:
 ATPG/SETUP/ ...> system [Unix command]

 To perform Kshell editing:

 ATPG/SETUP ...> set command editing -vi

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 Useful Tool and System Commands
 System commands that can be used within the tool
environment:
 setenv
 unsetenv
 Tool commands that help you to navigate the tool or interact
with the operating system:
 help — displays useful information for the specified command
 history — displays a list of previously-executed commands
 report environment — displays current values of many of the
most frequently uses “set …” commands
 report external simulator — displays the shell command the
tool will use to invoke an external simulator
 report resources — displays the machine resources used by the
active tool session
 report variables — displays user-defined variables and values
 report version data — displays the current software version
 system <os_command> — passes the specified command to the
OS.
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 Getting Help
 Command line — text-based command usage options or InfoHub
setup> HELp [command_name] [-manual]
(loads the reference manual for [command name].)

setup> HELp [command_name]

(echoes text-based [command_name] usage in the DFT shell.)

 InfoHub — HTML-based library of all DFT manuals

shell> mgcdocs
shell> testkompress -manual
shell> fastscan -manual

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 Accessing SupportNet Material
 Login required
 Documentation
 Release notes
 Process guides and
reference manuals
 Application notes
 Tech notes
 Software
 Releases
 Patches
 Open service requests
(SRs)

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 Customer Support
 SupportCenter by Country
http://supportnet.mentor.com/contacts/supportcenters/index.cfm
 DirectConnect North America 1-800-547-4303
 Monday–Friday, 6am - 5:30pm (PST)

 SupportNet
Website http://supportnet.mentor.com
 Additional Community Resources
– User2User
– Mentor Graphics Users’ Group (MUG)
– More users’ group at http://supportnet.mentor.com/community/
 Forums
 SupportNet news

 Mentor DFT website

http://www.mentor.com/products/silicon-yield/
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 Customer Support (Cont.)

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 Lab 1: Exploring the Help System

During this lab you will:

 Use commands to
 Access help from the UNIX/Linux shell.
 Load a design into Tessent FastScan.
 Search documentation using the Command Line Interface (CLI).

 Explore various ways to access help using InfoHub.

 Research command usage.
 Access “Getting Started with ATPG” in the documentation, an
introductory tutorial on ATPG.

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