SRI VENKATESWARA COLLEG OF ENGINEERING

(AUTONOMOUS)
TIRUPATI
DEPARTMENT OF
ELECTRONICS AND COMMUNICATION
ENGINEERING

Presentation on
Introduction to low power VLSI circuits and systems
By
Mr.P.Rajesh, M.Tech.,(Ph.D)
Assistant Professor
S.V.C.E-Tirupati
 COURSE OUTCOMES

CO1: Under stand the concepts of MOS transistors and electrical characteristics of
MOS, various power dissipation sources
CO2: Implement Low power design approaches for system level and circuit level
measures.
CO3: Design low power adders, multipliers and memories for efficient design of
systems
 UNIT I

• Introduction, Historical background, why low power, sources of

power dissipations, low power design methodologies.

• MOS Transistors: Introduction, the structure of MOS Transistor,

the Fluid model,Modes of operation of MOS Transistor, Electrical

characteristics of MOS Transistors, MOS Transistors as a switch.

 UNIT II-MOS Inverters

 Introduction, inverter and its characteristics,configurations,

inverter ratio in different situations, switching characteristics
delay parameters,driving parameters,driving large capacitive
loads.
MOS Combinational Circuits: introduction, Pass-Transistor
logic, Gate logic, MOS Dynamic Circuits.
 UNIT III
Sources of Power Dissipation
• Introduction, short-circuit powerdissipation,switching
power dissipation, glitching power dissipation, leakage
power dissipation.
Supply voltage scaling for low power: Introduction,
device features size scaling,architecture-level
approaches,voltage scaling,multilevel voltage scaling,
challenges,dynamic voltage and frequency scaling,
adaptive voltage scaling.
 UNIT IV-Minimizing Switched Capacitance:

• Introduction, system-level approaches,transmeta‟s

Crusoe processor, bus encoding, clock gating,
gated-clock FSMs, FSM state encoding,FSM
Partitioning, operand isolation, precomputation,
logic styles for low power.
 UNIT V
Minimizing Leakage Power
• Introduction, fabrication of multiple threshold
voltages,approaches for minimizing leakage
power, Adiabatic Logic Circuits, Battery-
Driven System, CAD Tools for Low Power
VLSI Circuits.
 Unit-1
Low power VLSI circuits and systems

Part-A
• Introduction
• Historical background
MOORE’S Law
 Why Low power
Changing Trend
Packaging and cooling cost
Increasing power density of VLSI circuits
Portable systems
Reliability
 sources of power dissipations
 low power design methodologies
 Introduction
• Design for low power has become nowadays one of the major concerns for
complex, very-large-scale-integration (VLSI) circuits.
• Deep submicron technology, from 130 nm onwards, poses a new set of
design problems related to the power consumption of the chip.
• As technology has shrunk to 90 nm and below, the leakage current has in-
creased dramatically.
• some 65-nm designs, leakage power is nearly as large as dynamic power.
• So it is becoming impossible to increase the clock speed of high-
performance chips as technology shrinks and the chip density increases, be-
cause the peak power consumption of these chips is already at the limit and
cannot be increased further.
• The objective of this subject is to provide Comprehensive coverage of
different aspects of low power circuit synthesis at various levels of design
hierarchy.
 Historical background

• The invention of transistor by William Shockley and his colleagues John

Bardeen and Walter Brattain at Bell Labo-ratories.
• The tremendous success of the transistor led to vigorous research activity
in the field of microelectronics.
• Gordon Moore, a member of Shockley’s team, founded Fairchild and later
Intel. Re-search engineers of Fairchild developed the first planner
transistor in the late 1950s, which was the key to the development of
integrated circuits (ICs) in 1959.
• The starting point was the year 1959—the year of production of the first
planner transistor. The other three points are based on the ICs made by
Fairchild in the early 1960s, including an IC with 32 components in
production in 1964. The last one was an IC to be produced in 1965 with 64
components
MOORE’S LAW
VLSI CIRCUITS
Technology growth graph
Technology growth
Technology growth
Landmark years of Semiconductor industry
SOURCES OF POWER DISSIPATION
 PART-B
MOS TRANSISTORS
• Introduction
• The structure of MOS Transistor
• The Fluid model
• Modes of operation of MOS Transistor
• Electrical characteristics of MOS
• Transistors, MOS Transistors as a switch
MOS TRANSISTORS
 DEPLETION-TYPE N-Channel MOSFET CONSTRUCTION
 The Drain (D) and Source (S)
connect to the to n-doped regions.

 These n-doped regions are

connected via an n-channel.

 This n-channel is connected to the

Gate (G) via a thin insulating layer
of SiO2.

 The n-doped material lies on a p-

n-Channel depletion- doped substrate that may have
type MOSFET an additional terminal
connection called Substrate
Dielectri (SS).
c
insulator
DEPLETION-TYPE N-Channel MOSFET :

 VGS = 0 and VDS is applied

across the drain to
source terminals.

 This results to attraction

of free electrons of the n-
channel to the drain, and
hence current flows.
.
 𝑉𝐺𝑆 is set at a negative voltage such
as
-1 V

 The negative potential at the gate

pressure electrons toward the p-type
substrate and attract the holes for the
p-type substrate.

 This will reduce the number of free

electrons in the n-channel available for
conduction.
 The more negative ,
𝑉𝐺𝑆
the
resulting level of drain the
current reduced. 𝐼𝐷
is
 When 𝑉𝐺 𝑆 is reduced to 𝑉𝑃
(pinch off voltage), then 𝐼𝐷 = 0𝑚𝐴.
 Ohmic region saturation region

pinch
off)

Transfer characteristics Drain V- I characteristics

When 𝑉𝐺𝑆 is reduced to 𝑉𝑃 (pinch off) {i.e 𝑉𝑃 = −6𝑉} then 𝐼𝐷 = 0𝑚𝐴.

For positive values of 𝑉𝐺𝑆, the positive gate will draw additional
electrons (free carriers from the p-type substarte and hence 𝐼𝐷
increases.)
DEPLETION-TYPE P-Channel MOSFET CONSTRUCTION
 P-CHANNEL JFET - characteristics

Transfer characteristics Drain V- I characteristics

ENHANCEMENT - TYPE MOSFET
ENHANCEMENT-TYPE N-Channel MOSFET CONSTRUCTION

 The Drain (D) and Source (S)

connect to the to n-doped
regions.

 The Gate (G) connects to the p-

doped substrate via a thin
insulating layer of SiO2

 There is no channel

 The n-doped material lies on a

p- doped substrate that may
have an additional terminal
connection
 For 𝑉𝐺𝑆 = 0, 𝐼𝐷 = 0(no channel)
 For 𝑉𝐷𝑆 some positive voltage and
𝑉𝐺𝑆
= 0, two reversed biased n-
junctions and no significant flow
between drain and source.

 For 𝑉𝐺𝑆 > 0 and 𝑉d𝑆 > 0, the positive

voltage at gate pressure holes to
enter deeper regions of the p-
substrate, and the electrons in p-
substrate and the electrons in p-
substrate will be attracted to the
positive gate.
 The level of 𝑉𝐺𝑆 that results in the
significant increase in drain current
in called:
THRESHOLD VOLTAGE (Vt)
 For 𝑉𝐺𝑆 < 𝑉𝑇, 𝐼𝐷 = 0𝑚𝑎
BASIC OPERATION OF THE E-TYPE MOSFET
Note:
The enhancement-type
MOSFET operates only in
the enhancement mode
 𝑉𝐺𝑆 is always positive
 As 𝑉𝐺𝑆 increases, 𝐼𝐷
increases
 As 𝑉𝐺𝑆 is kept constant and 𝑉𝐷𝑆 is
increased, then 𝐼𝐷 saturates (𝐼𝐷𝑆𝑆)
and the saturation level, 𝑉𝐷𝑆𝑠𝑎𝑡 is
reached.
 𝑉𝐷𝑆𝑠𝑎𝑡 can be calculated by

𝑉𝐷𝑠𝑎𝑡 = 𝑉𝐺𝑆 − 𝑉𝑇
 E-TYPE N-CHANNEL MOSFET TRANSFER CURVE

To determine 𝐼𝐷 given
𝑉𝐺𝑆: Where,
𝑉𝑇 is the threshold
voltage or voltage at
which the MOSFET
turns on.
𝑘, a constant, can be determined by using values at a specific point and
the formula:
ENHANCEMENT-Type P-Channel MOSFET CONSTRUCTION
E-TYPE P-CHANNEL MOSFET TRANSFER CURVE
 CHANNEL LENGTH MODULATION

• Channel length modulation is an effect in field

effect transistors, a shortening of the length of
the inverted channel region with increase in
drain bias for large drain biases. The result of
CLM is an increase in current with drain bias
and a reduction of output resistance.
CHANNEL LENGTH MODULATION
CHANNEL LENGTH MODULATION
Figure of merit
TRANS-CONDUCTANCE gm
Threshold voltage
Threshold voltage
Threshold voltage
BODY EFFECT
BODY EFFECT
MOS Transistor as a switch
MOS Transistor as a switch
NMOS AS A SWITCH
PMOS AS A SWITCH