• Designing a system on a chip

– Craft components from silicon rather than selecting

catalog parts
• ICs (chips) are batch fabricated
– Inexpensive unit cost
• Bugs are hard to fix!
– Extensive design verification needed

CMOS VLSI Design

• Automotive electronic systems
– A typical Chevrolet has 80 ICs (stereo systems, display panels, fuel
injection systems, smart suspensions, antilock brakes, airbags)
• Signal Processing (DSP chips, data acquisition
systems)
• Transaction processing (bank ATMs)
• PCs, workstations
• Medical electronics (artificial eye, implants)
• Multimedia

CMOS VLSI Design

• Transistor counts and IC densities continue
to grow!
– Moore’s Law-The number of transistors on an IC doubles every
1.5 years
– Intel x486: 1 million transistors (1989), PowerPC: 2-3 million
transistors (1994), Pentium: 3.1 million transistors (1994), DEC
Alpha: 10 million transistors (1995)-9 million in SRAM, Pentium IV
(2001): 42 million transistors
• Memory (DRAM) is the “technology
driver”

CMOS VLSI Design

 IC Designs can be Analog or Digital
 Digital designs can be one of three groups
 Full Custom
 Every transistor designed and laid out by hand

 ASIC (Application-Specific Integrated Circuits)

 Designs synthesized automatically from a high-level
language description
 Semi-Custom
 Mixture of custom and synthesized modules

CMOS VLSI Design

CMOS VLSI Design
Designer Tasks Tools

Define Overall Chip

Text Editor
Architect C/RTL Model C Compiler
Initial Floorplan

Behavioral Simulation RTL Simulator

Logic Logic Simulation Synthesis Tools
Designer Timing Analyzer
Synthesis
Datapath Schematics Power Estimator

Cell Libraries
Circuit Circuit Schematics Schematic Editor
Designer Circuit Simulation Circuit Simulator
Router
Megacell Blocks

Layout and Floorplan

Physical Place and Route Place/Route Tools
Designer Physical Design
Parasitics Extraction and Evaluation
DRC/LVS/ERC Tools

CMOS VLSI Design

Source: ARM

CMOS VLSI Design

 Some of the events which led to the
microprocessor
Photographs from “State of the Art: A photographic history of the
integrated circuit,” Augarten, Ticknor & Fields, 1983.
They can also be viewed on the Smithsonian web site,
http://smithsonianchips.si.edu/

CMOS VLSI Design

1930: “Method and 1933: “Device for controlling
apparatus for controlling electric current”, U. S. Patent
electric currents”, U.S. 1,900,018
Patent 1,745,175

CMOS VLSI Design

 1940: Ohl develops the PN Junction
 1945: Shockley's laboratory established
 1947: Bardeen and Brattain create point contact transistor
(U.S. Patent 2,524,035)

Diagram from patent application

CMOS VLSI Design

 1951: Shockley develops a junction transistor
manufacturable in quantity (U.S. Patent 2,623,105)

Diagram from patent application

CMOS VLSI Design

 1950s: Shockley in Silicon Valley
 1955: Noyce joins Shockley Laboratories
 1954: The first transistor radio
 1957: Noyce leaves Shockley Labs to form Fairchild with
Jean Hoerni and Gordon Moore
 1958: Hoerni invents technique for diffusing impurities into
Si to build planar transistors using a SiO2 insulator
 1959: Noyce develops first true IC using planar transistors,
back-to-back PN junctions for isolation, diode-isolated Si
resistors and SiO2 insulation with evaporated metal wiring
on top

CMOS VLSI Design

 1959: Jack Kilby, working at TI, dreams up the idea of a
monolithic “integrated circuit”
 Components connected by hand-soldered wires and isolated
by “shaping”, PN-diodes used as resistors (U.S. Patent
3,138,743)

Diagram from patent application

CMOS VLSI Design

 1961: TI and Fairchild introduce the first logic ICs ($50
in quantity)
 1962: RCA develops the first MOS transistor

Fairchild bipolar RTL Flip-Flop RCA 16-transistor MOSFET IC

CMOS VLSI Design

 1967: Fairchild develops the “Micromosaic” IC using CAD
 Final Al layer of interconnect could be customized for different
applications

 1968: Noyce, Moore leave Fairchild, start Intel

CMOS VLSI Design

 1970: Fairchild introduces 256-bit Static RAMs
 1970: Intel starts selling1K-bit Dynamic RAMs

Fairchild 4100 256-bit SRAM Intel 1103 1K-bit DRAM

CMOS VLSI Design

 1971: Intel introduces the 4004
 General purpose programmable computer instead of custom chip for
Japanese calculator company

CMOS VLSI Design

• CMOS: Complementary Metal Oxide
Silicon
– Based on voltage-controlled field-effect transistors (FETs)

• Other technologies: bipolar junction

transistors (BJTs), BiCMOS, gallium
arsenide (GaAs)
– BJTs, BiCMOS, ECL circuits are faster but CMOS consumes
lower power and are easier to fabricate
– GaAs carriers have higher mobility but high integration levels are
difficult to achieve in GaAs technology

CMOS VLSI Design

• Bipolar transistors
– npn or pnp silicon structure
– Small current into very thin base layer controls large
currents between emitter and collector
– Base currents limit integration density
• Metal Oxide Semiconductor Field Effect
Transistors
– nMOS and pMOS MOSFETS
– Voltage applied to insulated gate controls current
between source and drain
– Low power allows very high integration

CMOS VLSI Design

• Some manufacturing processes are tightly coupled to the
product, e.g. Buick/Chevy assembly line
• IC manufacturing technology is more versatile
• CMOS manufacturing line can make circuits of any type by
changing some basic tools called masks
– The same plant can manufacture both microprocessors and microwave controllers by
simply changing masks
• Silicon wafers: raw materials of IC manufacturing
IC
Test
structure Wafer

CMOS VLSI Design

In 1965, Gordon Moore noted that the
number of transistors on a chip doubled every
18 to 24 months.
He made a prediction that semiconductor
technology will double its effectiveness every
18 months

CMOS VLSI Design

 • 1965: Gordon Moore plotted transistor on each chip
– Fit straight line on semilog scale
– Transistor counts have doubled every 26 months

1,000,000,000

100,000,000
Integration Levels
Pentium 4

SSI:
Pentium III
10,000,000 Pentium II
Pentium Pro 10 gates
Transistors

Pentium
Intel486
1,000,000

1000 gates
Intel386
80286
100,000
8086
10,000

MSI: 10,000 gates

8080
8008
4004
1,000

1970 1975 1980 1985 1990 1995 2000

LSI: > 10k gates
VLSI:
Year

CMOS VLSI Design

• Many other factors grow exponentially
– Ex: clock frequency, processor performance
10,000

1,000 4004

8008

8080
Clock Speed (MHz)

100 8086

80286

Intel386

10 Intel486

Pentium

Pentium Pro/II/III

1 Pentium 4

1970 1975 1980 1985 1990 1995 2000 2005

Year

CMOS VLSI Design

CMOS VLSI Design
 1 Billion
K Transistors
1,000,000

100,000
Pentium® III
10,000 Pentium® II
Pentium® Pro
1,000 Pentium®
i486
100 i386
80286
10 8086
Source: Intel
1
1975 1980 1985 1990 1995 2000 2005 2010
Projected
CMOS VLSI Design
Courtesy, Intel
CMOS VLSI Design
 100
Die size (mm)

P6
486 Pentium ® proc
10 386
286
8080 8086
8085 ~7% growth per year
8008
4004 ~2X growth in 10 years

1
1970 1980 1990 2000 2010
Year

Die size grows by 14% to satisfy Moore’s Law

CMOS VLSI Design

Courtesy, Intel
 10000
Doubles every
1000
2 years
Frequency (Mhz)

100 P6
Pentium ® proc
486
10 8085 386
8086 286
1 8080
8008
4004
0.1
1970 1980 1990 2000 2010
Year
Lead Microprocessors frequency doubles every 2 years

CMOS VLSI Design

Courtesy, Intel
 100

P6
Pentium ® proc
Power (Watts)

10
486
8086 286
386
8085
1 8080
8008
4004

0.1
1971 1974 1978 1985 1992 2000
Year

Lead Microprocessors power continues to increase

CMOS VLSI Design

Courtesy, Intel
 100000
18KW
10000 5KW
1.5KW
Power (Watts)

1000 500W
Pentium® proc
100
286 486
10 8086 386
8085
8080
8008
1 4004

0.1
1971 1974 1978 1985 1992 2000 2004 2008
Year

Power delivery and dissipation will be prohibitive

CMOS VLSI Design

Courtesy, Intel
 10000
Rocket
Power Density (W/cm2)

Nozzle
1000
Nuclear
100
Reactor

8086
10 4004 Hot Plate P6
8008 8085 386 Pentium® proc
286 486
8080
1
1970 1980 1990 2000 2010
Year

Power density too high to keep junctions at low temp

CMOS VLSI Design

Courtesy, Intel
 “Microscopic Problems” “Macroscopic Issues”
• Time-to-Market
• Ultra-high speed design
• Interconnect • Millions of Gates
• High-Level Abstractions
• Noise, Crosstalk
• Reuse & IP: Portability
• Reliability, Manufacturability
• Predictability
• Power Dissipation
• etc.
• Clock distribution.

Everything Looks a Little

…and There’s a Lot of Them!
Different
?
CMOS VLSI Design
• Interconnect-centric design
– Capacitive coupling, inductance effects, delay modeling
• Power densities, power grid design, leakage
– 80 W/cm2  100 W/cm2
• Nuclear reactor: 150 W/cm2
– 80% increase in power density per generation (voltage
scales by 0.8)
– 225% increase in current density
– 1.3V power supply leads to 60W power with 60A
sustained current
• 2X the current (surge) in your car’s alternator
• Statistical design (P,V,T)

CMOS VLSI Design

 Technology shrinks by 0.7/generation
 With every generation can integrate 2x more
functions per chip; chip cost does not increase
significantly
 Cost of a function decreases by 2x
 But …
 How to design chips with more and more functions?
 Design engineering population does not double every two years…

 Hence, a need for more efficient design methods

 Exploit different levels of abstraction

CMOS VLSI Design

 SYSTEM

MODULE

GATE

CIRCUIT

DEVICE
G
S D
n+ n+

CMOS VLSI Design

 How to evaluate performance of a digital circuit
(gate, block, …)?
 Cost
 Reliability
 Scalability
 Speed (delay, operating frequency)
 Power dissipation
 Energy to perform a function

CMOS VLSI Design

 NRE (non-recurrent engineering) costs
 design time and effort, mask generation
 one-time cost factor

 Recurrent costs
 silicon processing, packaging, test
 proportional to volume
 proportional to chip area

CMOS VLSI Design

CMOS VLSI Design
 Single die

Wafer

Going up to 12” (30cm)

From http://www.amd.com CMOS VLSI Design

 cost:
¢-per-transistor
1
0.1 Fabrication capital cost per transistor (Moore’s law)
0.01
0.001
0.0001
0.00001
0.000001
0.0000001
1982 1985 1988 1991 1994 1997 2000 2003 2006 2009 2012

CMOS VLSI Design

 No. of good chips per wafer
Y  100%
Total number of chips per wafer
Wafer cost
Die cost 
Dies per wafer  Die yield
  wafer diameter/2 2   wafer diameter
Dies per wafer  
die area 2  die area

CMOS VLSI Design

 
 defects per unit area  die area 
die yield  1  
  
 is approximately 3

die cost  f (die area)4

CMOS VLSI Design