Operatin
Unit-1:
g Chapter
Systems:
Internals 1 Computer
and
Design System
Principles O
verview By William
Stallings
Operating System as a Resource Manager
Exploits
the hardware resources of one
or more processors ( primary memory,
secondary memory, I/O, File)
Providesa set of services to system
users which manages resources &
processes.
Manages secondary memory and I/O
devices.
Basic Elements of Hardware
• Hardware which are managed by OS.
I/O
Processor Modules
Main System
Memory Bus
Controls the Performs the
operation of data
the computer processing
functions
Referred to
as the
Central
Processing Unit
(CPU)
Functionality of Processor
• Processor Executes statements/ instructions
which are written within our program with the
help of Dispatcher (part of OS) .
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Main Memory(Primary memory)
Volatile/
after execution of
process, data will be deleted
from P.M.
Contentsof the memory is lost
when the computer is shut
down
Referred
to as real memory
or primary memory
I/O Modules
storage (e.g.
hard
Moves data drive)
between
the
computer communications
and equipment
external
environmen termina
ts such as: ls
Provides for communication
among processors, main
memory, and I/O modules
Establish communication, data
are tranferred through System
bus.
CPU Main Memory
0
System 1
PC MAR Bus 2
Instruction
Instruction
Instruction
IR MBR
I/O AR
Data
Execution
unit Data
I/O BR Data
Data
I/O Module n-2
n-1
PC = Program counter
IR = Instruction register
Buffers
MAR = Memory address register
MBR = Memory buffer register
I/O AR = Input/output address register
I/O BR = Input/output buffer register
Figure 1.1 Computer Components: Top-Level View
Microprocessor
Invention that brought about
desktop and handheld
computing
Processor on a single chip
Fastest general purpose
processor
Multiprocessors
Each chip (socket) contains
GUI
Provide efficient computation on
arrays of data using Single-
Instruction Multiple Data (SIMD)
techniques
Used for general numerical
processing
Physics simulations for games
Computations on large
Deal with streaming signals
such as audio or video
Used to be embedded in
devices like modems
Encoding/decoding speech and
video (codecs)
Support for encryption and
security
System on a Chip (SoC)
Tosatisfy the requirements of
handheld devices, the
microprocessor is giving way to
the SoC
Components such as DSPs,
GPUs, codecs and main
memory, in
addition to the CPUs and caches,
Instruction Execution by OS with the help of
Processor
A program consists of a set of
instructions stored in Primary
memory (Process Image)
processor reads
(fetches) processor
instructions from executes each
memory instruction
Two steps
Fetch Stage Execute Stage
Fetch Next Execute
START HALT
Instruction
Instruction
Figure 1.2 Basic Instruction Cycle
The processor fetches the
instruction from Primary memory.
Program counter (PC) (Part of
Processor) holds address of the
instruction to be fetched next by OS.
PC is incremented after each fetch
Fetch Stage Execute Stage
Memory CPU Memory CPU
Registers Registers
300 1 9 4 0 3 0 0 PC 300 1 9 4 0 3 0 1 PC
301 5 9 4 1 AC 301 5 9 4 1 000 3 AC
302 2 9 4 1 1 9 4 0 IR 302 2 9 4 1 194 0 IR
•
• 940 0•• 0 0 3 940 0 0 0 3
941 0 0 0 2 941 0 0 0 2
Step 1 Step 2
Memory CPU Registers CPU Registers
300 1 9 4 0 3 0 1 PC 300 1 9 4 0 3 0Memory
2 PC
301 5 9 4 1 0 0 0 3 AC 301 5 9 4 1 000 5 AC
302 2 9 4 1 5 9 4 1 IR 302 2 9 4 1 594 1 IR
• •
• •
940 0 0 0 3 940 0 0 0 3 3+2=5
941 0 0 0 2 941 0 0 0 2
Step 3 Step 4
Memory CPU Registers Memory CPU Registers
300 1 9 4 0 3 0 2 PC 300 1 9 4 0 3 0 3 PC
301 5 9 4 1 0 0 0 5 AC 301 5 9 4 1 0 0 0 5 AC
302 2 9 4 1• 2 9 4 1 IR 302 2 9 4 1• 2 9 4 1 IR
• •
940 0 0 0 3 940 0 0 0 3
941 0 0 0 2 941 0 0 0 5
Step 5 Step 6
Figure 1.4 Example of Program Execution
(contents of memory and registers in hexadecimal)
Interrupt
• Ready-> Running . At the time of execution of a process in running state,
higher priority process is waiting in Ready queue, OS will interrupt running
state process and instruct to release processor & allow to dispatch higher
Priority ready state process to running state.
Interrupt the normal sequencing
of the processor
•
Provided to improve processor
utilization
most I/O devices are slower than the
processor
processor must pause to wait for device
wasteful use of the processor
Table 1.1 Classes of Interrupts
Progra Generated by some condition that occurs as a
m result of an instruction execution, such as
arithmetic overflow, division by zero, attempt to
and
execute
reference
an illegal
outside
machine
a user's
instruction,
allowed
memory space.
Time Generated by a timer within the processor. This
r allows the operating system to perform certain
functions on a regular basis. After completion of
time-slice, process will move from running to
I/ O ready.
Generated by an I/O controller, to signal normal
completion of an operation or to signal a variety
of error conditions.
Hardwar Generated by a failure, such as power failure or
e failure memory parity error.
User I/O
Program Program
1 4
I/O
Command
Figure WRITE
5
1.5a 2
END
Flow of
Control
Withou
WRITE
t 3
Interrup WRITE
ts (a) No interrupts
User I/O
Program Program
1 4
I/O
Command
WRITE
2a
Figure Interrupt
1.5b
2b
Handler
WRITE 5
Short I/O 3a
END
Wait
3b
WRITE
(b) Interrupts; short I/O wait
User I/O
Program Program
1 4
I/O
Command
WRITE
Figure 2
1.5c Interrupt
Handler
5
Long I/O
WRITE
END
Wait 3
WRITE
(c) Interrupts; long I/O wait
User Program Interrupt Handler
i
Interrupt
occurs here i+1
Figure 1.6 Transfer of Control via Interrupts
Fetch Stage Execute Stage Interrupt Stage
Interrupts
Disabled
Check for
Fetch next Execute interrupt;
START instruction instruction initiate interrupt
Interrupts
handler
Enabled
HALT
Figure 1.7 Instruction Cycle with Interrupts
Time
1 1
4 4
I/O operation
I/O operation;
processor waits
2a concurrent with
processor executing
5 5
2b
2
4
I/O operation
4 3a concurrent with
processor executing
I/O operation;
processor waits 5
5 3b
(b) With interrupts
3
(a) Without interrupts
Figure 1.8 Program Timing: Short I/O Wait
Time
1 1
4 4
I/O operation; 2 I/O operation
processor waits concurrent with
processor executing;
then processor
waits
5
5
2
4
4
3 I/O operation
concurrent with
I/O operation; processor executing;
processor waits then processor
waits
5
5
3 (b) With interrupts
(a) Without interrupts
Figure 1.9 Program Timing: Long I/O Wait
Hardware Software
Device controller or
other system hardware
issues an interrupt
Save remainder of
process state
information
Processor finishes
execution of current
instruction
Process interrupt
Processor signals
acknowledgment
of interrupt
Restore process state
information
Processor pushes PSW
and PC onto control
stack
Restore old PSW
and PC
Processor loads new
PC value based on
interrupt
Figure 1.10 Simple Interrupt Processing
T–M T–M
Y N+1
Control Control
Stack Stack T
T N+1 Y+L+1
Program Program
Counter Counter
Y Start Y Start
Interrupt General Interrupt General
Service Registers Service Registers
Y+L Return Routine T Y+L Return Routine T–M
Stack Stack
Pointer Pointer
Processor Processor
T–M T
N User's N User's
N+1 N+1
Program Program
Main Main
Memory Memory
(a) Interrupt occurs after instruction
(b) Return from interrupt
at location N
Figure 1.11 Changes in Memory and Registers for an Interrupt
Multiple Interrupts
An interrupt occurs
while another Two approaches:
interrupt is being
processed
• e.g. receiving data • disable interrupts
from a while an interrupt
communications is being processed
line and printing • use a priority
results at the same scheme
time
Memory
• Without utilization of Primary memory, processor can not execute any
instruction with the help of OS.
Major constraints in memory
amount
speed
expense
Memory must be able to keep up with the
processor
Cost of memory must be reasonable in
relationship to the other components
Memory Relationships
Greater
Faster capacity
access = smaller cost
time Greater
per bit capacity =
=
greater slower
cost access
speed
per bit
Going down Inb
g-
Re rs
iste
e
the
Me oard ch
m Ca
or y in
Ma ory
em
M
hierarchy: Ou
tb
Sto oard gn OM
etic
Dis
k
r
age Ma D-R W
C -R
CD -RW
VD AM
D R
V D- y
D lu-Ra
decreasing cost
B
per bit
Of e
f- Tap
Sto line etic
r
age gn
Ma
increasing
capacity
increasing
access time Figure 1.14 The Memory Hierarchy
Secondary
Memor
y
Also referred to
as auxiliary
memory
• external
• nonvolatile
• used to store
program and data
files
Invisible to the OS
Interacts with other memory management
hardware
Processor must access memory at least once per
instruction cycle
Processor execution is limited by memory cycle
time
Exploit the principle of locality with a small, fast
memory
Block Transfer
Word Transfer
CPU Cache Main Memory
Fast Slow
(a) Single cache
Level 1 Level 2 Level 3 Main
CPU
(L1) (L2) cache
(L3)
cache cache Memory
Fastest Fast
Less Slow
fast
(b) Three-level cache organization
Figure 1.16 Cache and Main Memory
Line Memory
Number Tag Block address
0 0
1 1
2 2 Block 0
3 (K words)
-1
Block Length
(K Words)
(a) Cache
Block M – 1
2n - 1
Word
Length
(b) Main memory
Figure 1.17 Cache/Main-Memory Structure
START
RA - read address
Receive address
RA from CPU
Is block No Access main
containing RA memory for block
in cache? containing RA
Yes
Fetch RA word Allocate cache
and deliver slot for main
to CPU memory block
Load main
Deliver RA word
memory block
to CPU
into cache
slot
DONE
Figure 1.18 Cache Read Operation
cache
size
number
of block
cache size
levels
Main
categori
es are:
writ mappin
e g
polic functio
y n
replaceme
nt
algorith
m
Programmed I / O
The I/O module performs the requested
action then sets the appropriate bits in
the I/O status register
The processor periodically checks the
status of the I/O module until it
determines the instruction is complete
With programmed I/O the performance
level of the entire system is severely
degraded
Direct Memory Access
(DMA)
∗ Performed by a separate module on the
system bus or incorporated into an I/O module
When the processor wishes to read or write
data it issues a command to the DMA
module containing:
• whether a read or write is requested
• the address of the I/O device involved
• the starting location in memory to
read/write
• the number of words to be read/written
Transfers the entire block of data
directly to and from memory without
going through the processor
processor is involved only at the beginning and
end of the transfer
processor executes more slowly during a
transfer when processor access to the bus is
required
More efficient than interrupt-
driven or programmed I/O
Summary
Cache memory
BasicElements Motivation
Evolution of the Cache principles
microprocessor Cache design
Instruction Direct memory access
execution Multiprocessor and
Interrupts • multicore organization
Interrupts and the Symmetric
instruction cycle • multiprocessors
Interrupt processing Multicore computers
Multiple interrupts
The memory hierarchy
