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8 Bit CPU Design Document

8 Bit CPU Design Document

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Hijab Ejaz
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27 views

8 Bit CPU Design Document

8 Bit CPU Design Document

Uploaded by

Hijab Ejaz
Copyright
© © All Rights Reserved
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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8 Bit CPU

Design
Document
By Hijab Ejaz
29247
Registers

Memory Cell holds 1 bit of data.

Loop enable data to be stored even when WE is off

Made from DFlipFlop


4- and 8-Bit Registers

Connect the respective number of memory cells


to make the registers
Program Counter
This program counter counts to the to the highest
Possible value that 4 bits can hold, which is 0-15. This
Is convenient when traversing our RAM which has 0-15
Memory locations.

This counter has the option for a limit. This will be used
In our step counter. The limit is incremented since the
Counter needs to reach that limit and then go to zero.
ALU

My ALU performs 9 operations

The answer to each operation is fed into a multiplexer that choose the desired answ
With the help of 4 control lines
ALU – 8-Bit Addition 4-Bit Adder
Addition is built up by the following

1-Bit Adder

2s compliment

8-Bit Adder
ALU-Subtraction
I had to make a separate subtraction circuit since the 2s compliment had a
Carry out that I was not able to correctly transfer to the second 4-bit subcircuit

2s compliment

Although I made cin and cout


To cascade the carry, complimenting
00000000 would still give 0001000
AND, OR & XOR
Increment and Decrement

Increment is just 8 1-bit adders cascading. Decrement is also the same but now we are adding
8-bit number is added with 00000001 -1. 2s compliment of 00000001 -> 11111110 -> 1111111
Left-Shift and Right-Shift
First 2 bits go into 0 and 1. This shifts them
to left. The next two bits will become the
2nd and 3rd bit.
Left-Shift

Right-Shift

Right-Shift can be one in the same way, j=only difference being that we are
2-bit Left Shift starting from the 2 MSB and hence the last 2 will go into 0 and 1 and then
the second last will be propagated to the third last.
I had originally planned for 16 operations in the ALU but then when I starting
ALU-MUX working on the opcodes I realized that would need a higher level of complexit
Hence some inputs in the MUX are empty.

I started with a 4 to 1 MUX.

Then used that to make a 16 to 1 MUX

This works by choosing 4 outputs using the first 2


control lines and then chooses between these 4
using the last 2 control lines
Control Units
The first logical problem I ran into was that the control unit had to fetch instructions independently, withou
having the opcode as an input. How will the instruction be fetched when the instruction contains the fetch
command in the first place? So, I made a fetch unit that was separate from the execute unit. The fetch uni
operated by the step-counter.

This is where the limited program counter comes in. It will be limited
to 7 or 111. From 000-100 the instruction will be fetched from the ram
and from 101-111 the instruction will be executed.
I have arranged the data in the RAM by using even and odd addresses.
Fetch Unit At the even address, the opcode is stored and at the next odd address
the data to be operated on is stored.

What gates the fetch unit will open in what clock cycle

The opcode reaches the instruction register which is feeding into the
execute unit.

The data reaches the memory bus register

Circuit created using combinational analysis


Execute Unit What gates it opens on what step counter

OPCodes and what they do


Execute units sends
control lines to ALU
to perform the
desired operation

Direct data lines from


RegA and RegB to ALU
since we cannot send two
bytes to the ALU simultaneously
through the bus. Furthermore, sending data one by one
would require us to turn on WE ALU twice and that would
flush the previously stored value.
Putting it all together
Note that the limit of the step counter mus
be set to 7 before starting the CPU
otherwise the odd even thing won’t work

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