Flip-Flops

Module-4
Introduction

● The outputs of the digital circuits considered

previously depends entirely on their inputs.
● If an input changes state, output may also change
state.
● However, There are requirements for a digital device
or circuit whose output will remain unchanged, once
set, even if there is a change in input level(s).
● Such a device could be used to store a binary
number.
● A flip-flop is one such circuit, and the
characteristics of the most common types of
flip-flops used in digital systems are
considered in this chapter.
● Flip-flops are used in the construction of
registers and counters, and in numerous
other applications.
RS FLIP-FLOPS

● Any device or circuit that has two stable

states is said to be bistable.
● For instance, a toggle switch has two stable
states. It is either up or down, depending on
the position of the switch as shown in Fig.
8.la.
 RS FLIP-FLOPS
● A flip-flop is a bistable electronic circuit that has
two stable states-that is, its output is either 0 or
+5 V dc as shown in Fig. 8.1 b.
● The flip-flop also has memory since its output will
remain as set until something is done to change it.
RS FLIP-FLOPS

● The flip-flop (or the switch) can be regarded as

a memory device. In fact, any bistable device
can be used to store one binary digit (bit).
● When the flip-flop has its output set at O V dc,,
it can be regarded as storing a logic O and when
its output is set at + 5 V dc, as storing a logic l.
● The flip-flop is often called a latch, since it will
hold, or latch, in either stable state.
 RS FLIP-FLOPS-Basic Idea
● One of the easiest ways to construct a flip-flop is to
connect two inverters in series as shown in Fig.
8.2a.
● The line connecting the output of inverter B (INV B)
back to the input of inverter A (INV A) is referred to
as the feedback line.
 RS FLIP-FLOPS-Basic Idea

● For the moment, remove the feedback line and

consider V1 as the input and V3 as the output as
shown in Fig. 8.2b.
● There are only two possible signals in a digital system, and in
this case we will define L = 0 = 0 V de and H = 1 = + 5 V dc.

● If V1 is set to O V dc, then V3 will also be O V dc.

● Once the input of INVA is grounded, the output of INV B will go

low and can then be used to hold the input of INV A low by
using the feedback line. This is one stable state-V3 = 0 Vdc.
RS FLIP-FLOPS-Basic Idea

● If V1 is +5 Vdc, V3 will also be +5 Vdc as

seen in Fig. 8.2c. The feedback line can again
be used to hold Vi at + 5 V de since V3 is also
at + 5 V de. This is then the second stable
state- V3 = + 5 V de.
 NOR-Gate Latch
● The basic flip-flop shown in Fig. 8.2a can be
improved by replacing the inverters with either
NAND or NOR gates.
● Two 2-input NOR gates are connected in Fig. 8.3a
to form a flip-flop.
● Notice that if the two inputs labeled R and S are
ignored, this circuit will function exactly as the
one shown in Fig. 8 .. 2a.
 NOR-Gate Latch
● This circuit is redrawn in a more conventional form in
Fig. 8.3b.
● The flip-flop actually has two outputs, defined in
more general terms as Q and Q’.
● It should be clear that regardless of the value of Q,
its complement is Q’.
● There are two inputs to the flip-flop defined as R and
S.
● The input/output possibilities for this RS flip-flop are
NOR-Gate Latch
NOR-Gate Latch
● The standard logic symbols for an RS flip-flop are
shown in Fig. 8.6 along with its truth table. The
truth table is necessary since it describes exactly
how the flip-flop functions.
Use the pinout diagram for a 54/7427 triple 3-input NOR
gate and show how to connect a simple RS flip-flop.
 NAND-Gate latch

A slightly different latch can be constructed by using

NAND gates as shown in Fig. 8.7.
The truth table for this NAND-gate latch is different
from that for the NOR-gate latch.
We will call this latch an R’S’ flip-flop.
To understand how this circuit functions, recall that a
low on any input to a NAND gate will force its output
high.
GATED FLIP-FLOPS

● Two different methods for constructing an RS

flip-flop were discussed in Sec. 8.1.

● The NOR-gate realization in Fig. 8.3b is an

exact equivalent of the NAND-gate realization
in Fig. 8.8a, and they both have the exact
same symbol and truth table as given in Fig.
8.6.
● Both of these RS flip-flops, or latches, are
said to be transparent; that is, any change in
input information at R or S is transmitted
immediately to the output at Q and Q’
according to the truth table.
 Clocked RS Flip-Flops

● The addition of two AND gates at the R and S

inputs as shown in Fig. 8.1 1 will result in a flip-
flop that can be enabled or disabled.
Clocked RS Flip-Flops

● When the ENABLE input is low, the AND gate

outputs must both be low and changes in
neither R nor S will have any effect on the
flip-flop output Q. The latch is said to be
disabled.

● When the ENABLE input is high, information

at the R and S inputs will be transmitted
directly to the outputs. The latch is said to be
Clocked RS Flip-Flops

● The output will change in response to input

changes as long as the ENABLE is high.

● When the ENABLE input goes low, the

output will retain the information that was
present on the input when the high-to-low
transition took place.
Clocked RS Flip-Flops

● In this fashion, it is possible to strobe or clock the

flip-flop in order to store information (set it or reset
it) at any time, and then hold the stored
information for any desired period of time.

● This flip-flop is called a gated or clocked RS

flip:flop.
● There are now three inputs--R, S, and the ENABLE or
CLOCK input, labeled EN. Notice also that the truth-table
output is not simply Qn, but Qn+ 1
● This is because we must consider two different instants
in time: the time before the ENABLE goes low Qn and
the time just after ENABLE goes low Qn+ 1.
● When EN= 0, the flip-flop is disabled and R and S have
no effect; thus the truth table entry for R and S is X
(don't care).
Clocked D Flip-Flops

● The RS flip-flop has two data inputs, R and S.

● To store a high bit, you need a high S; to store a low bit, you need a high
R.
● Generation of two signals to drive a flip-flop is a disadvantage in many
applications.
● Furthermore, the forbidden condition of both R and S high may occur
inadvertently. This has led to the D flip-flop, a circuit that needs only a
single data input.
● Figure 8.14 shows a simple way to build a D (Data) flip-flop. This flip-flop
is disabled when EN is low, but is transparent when EN is high.
● D flip flop is disabled when EN is low, but is transparent when EN is
high.
● The action of the circuit is straightforward, as follows- when EN is
low,both AND gates are disabled and D changes its value Without
affecting the value of Q.
● When EN is high, both AND gates are enabled
● Q is forced to be equal of D.
● When EN again goes low, Q retain or stores the last vale of D.
Clocked D Flip-Flops
Clocked D Flip-Flop
D FLIP FLOP

● Four D latches are driven by the same clock signal.

● When the clock goes high, input data is loaded into the flip-flops and appears at the
output.
● Then when the clock goes low, the output retains the data.
● For instance,suppose that the data input is 0111.
● When the clock goes high, this word is loaded into the D latches , resulting in an
output of 0111.
● After the clock goes low, the output data is retained or stores.
● As long as the clock is low, the D values can change without affecting the Q values
 EDGE-TRIGGERED RS flip-flops

● The simple latch-type flip-flops presented in Sec. 8.1 are completely

transparent; that is, the output Q immediately follows any change of state at
the input (R, S, or D).

● The gated or clocked RS and D flip-flops in Sec. 8.2 might be considered semi
transparent, that is, the output Q will change state immediately provided that
the EN input is high. If any of these flip-flops are used in a synchronous system,
care must be taken to ensure that all flip-flop inputs change state in
synchronism with the clock.

● One way of resolving the problem for gated flip-flops is to use edge triggered
Positive-Edge-Triggered RS Flip-flops
Use the positive-edge-triggered RS flip-flop truth table
to explain Q changes of state with time in Fig. 8.18d.
Negative-Edge-Triggered RS Flip-Flops
Use the negative-edge-triggered RS flip-flop truth table to
explain Q changes of state with time in Fig. 8.20.
EDGE-TRIGGERED D flip-flops
EDGE-TRIGGERED D flip-flops
EDGE-TRIGGERED D flip-flops

● Depressing the RESET button will set Q to I with the first PT of the clock. Q will remain
high as long as the button is held closed.

● The first PT of the clock after releasing the button will set Q according to the D input.
Furthermore, the OR gates allow us to slip in a high PRESET or a high CLEAR when desired.

● A high PRESET forces Q to equal 1; a high CLEAR resets Q to 0.

● The PRESET and CLEAR are called asynchronous inputs because they activate the flip-flop
independently of the clock. On the other hand, the D input is a synchronous input because
it has an effect only with PTs of the clock.
EDGE-TRIGGERED D flip-flops
● Figure 8.23a is the IEEE symbol for a positive-edge-triggered D flip-flop. The clock
input has a small triangle to serve as a reminder of edge triggering. When you see
this symbol, remember what it means; the D input is sampled and stored on PTs of
the clock.

● Sometimes, triggering on NTs of the clock is better suited to the application. In this
case, an internal inverter can complement the clock pulse before it reaches the
AND gates. Figure 8.23b is the symbol for a negative-edge-triggered D flip-flop. The
bubble and triangle symbolize the negative-edge triggering

● Figure 8.23c is another commercially available D flip-flop (the 54/74175 or 54/74LS

175). Besides having positive-edge triggering, it has an inverted CLEAR input This
EDGE-TRIGGERED D flip-flops
EDGE-TRIGGERED JK- FLIP FLOP

● Setting R = S = I with an edge-triggered RS flip-flop forces both Q

and Q’ to the same logic level.
● This is an illegal condition, and it is not possible to predict the final
state of Q.
● The JK flip-flop accounts for this illegal input, and is therefore a
more versatile circuit.
● Among other things, flip-flops can be used to build counters.
● Counters can be used to count the number of PTs orNTs of a clock.
● For purposes of counting, the JK flip-flop is the ideal element to
use.
● There are many commercially available edge-triggered JK flip-flops.
Positive-Edge-Triggered J K Flip-Flops

● In Fig. 8.24, the pulse-forming box changes the clock into a

series of positive pulses, and thus this circuit will be
sensitive to PTs of the clock.
● The basic circuit is identical to the previous positive-edge-
triggered RS flip-flop, with two important additions:

1. The Q output is connected back to the input of the lower

AND gate.

2. The Q output is connected back to the input of the upper

AND gate. This cross-coupling from outputs to inputs
changes the RS flip-flop into a JK Flip Flop.
Positive-Edge-Triggered J K Flip-Flops

The previous S input is now labeled J, and the previous R input is

labeled K. Here's how it works:

● When J and K are both low, both AND gates are disabled.
Therefore, clock pulses have no effect.
● This first possibility is the initial entry in the truth table. As
shown, when J and K are both Os, Q retains its last value.
Positive-Edge-Triggered J K Flip-Flops
Positive-Edge-Triggered J K Flip-Flops

● When J is low and K is high, the upper gate is disabled, so

there's no way to set the flip-flop. The only possibility is reset.

● When Q is high, the lower gate passes a RESET pulse as soon as

the next positive clock edge arrives.

● This forces Q to become low (the second entry in the truth

table). Therefore, J = 0 and K = I means that the next PT of the
clock resets the flip-flop (unless Q is already reset).
Positive-Edge-Triggered J K Flip-Flops

● When J is high and K is low, the lower gate is disabled, so it's

impossible to reset the flip-flop. But you can set the flip flop as
follows.

● When Q is low, Q’ is high; therefore, the upper gate passes a SET

pulse on the next positive clock edge.

● This drives Q into the high state (the third entry in the truth table).
As you can see, J = 1 and K = 0 means that the next PT of the
clock sets the flip-flop (unless Q is already high).
Positive-Edge-Triggered J K Flip-Flops

● When J and K are both high (notice that this is the forbidden state
with an RS flip-flop), it's possible to set or reset the flip-flop.

● If Q is high, the lower gate passes a RESET pulse on the next PT.
On the other hand, when Q is low, the upper gate passes a SET
pulse on the next PT.

● Either way, Q changes to the complement of the last state (see the
truth table). Therefore, J = I and K = I mean the flip-flop will toggle
(switch to the opposite state) on the next positive clock edge.
JK MASTER-SLAVE FLIP-FLOPS
The symbol for a 7476 master-slave flip-flop is shown in Fig.
8.29.

Either it can be preset to Q = H by taking PR low, or it can be

reset to Q = L by taking CLR low.

These two inputs take precedence over all other signals!

The symbol appearing next to the Q and the Q outputs is the

IEEE designation for a postponed output. In this case, it means
Q does not change state until the clock makes an NT.
The master is set according to J and K while the clock is high; the
contents of the master are then shifted into the slave (Q
changes state) when the clock goes low.

This particular flip-flop might be referred to as pulse-triggered, to

distinguish it from the edge-triggered flip-flops previously
discussed.
Switch Contact Bounce Circuits
In nearly every digital system there will be occasion to use mechanical
contacts for the purpose of conveying an electrical signal; examples of
this are the switches used on the keyboard of a computer system.
In each case, the intent is to apply a high logic level (usually +5 Vdc)
or a low logic level (0 Vdc).
The single-pole single- throw (SPST) switch shown in Fig. 8.3 a is one
such example.
When the switch is open, the voltage at point A is +5 V de; when the
switch is closed, the voltage at paint A is O V de.
Ideally, the voltage waveform at A should appear as shown in Fig. 8.31
b as the switch is moved from open to closed, or vice versa.
In actuality, the waveform at point A will appear more or less as shown in
Fig. 8.31 c, as the result of a phenomenon known as contact bounce.
Any mechanical switching device consists of a moving contact arm
restrained by some sort of a spring system. As a result, when the
arm is moved from one stable position to the other, the arm
bounces, much as a hard ball bounces when dropped on a hard
surface.
The number of bounces that occur and the period of the bounce differ for
each switching device. Notice carefully that in this particular instance,
even though actual physical contact bounce occurs each time the switch is
opened or closed, contact bounce appears in the voltage level at point A
only when the switch is closed.
A Simple RS latch Debounce Circuit
The RS latch in Fig. 8.32 will remove any contact bounce due to the switch. The output (Q) is
used to generate the desired switch signal.

When the switch is moved to position H, R = 0 and S = 1. Bouncing occurs at the S input due
to the switch. The flip-flop "sees" this as a series of high and low inputs, settling with a high
level. The flip-flop will immediately be set with Q = 1 at the first high level on S.

When the switch bounces, losing contact, the input signals are R = S = 0, therefore the flip-
flop remains set (Q = 1).

When the switch regains contact, R = 0 and S = 1; this causes an attempt to again set the flip-
flop. But since the flip-flop is already set, no changes occur at Q.

The result is that the flip-flop responds to the first, and only to the first, high level at its S
input, resulting in a "clean" low-to-high signal at its output (Q).
When the switch is moved to position L, S = 0 and R = 1. Bouncing occurs
at the R input due to the switch. Again, the Debounce circuit flip-flop
"sees" this as a series of high and low inputs.

It simply responds to the.first high level, and ignores all following

transitions. The result is a "clean" high-to-low signal at the flip-flop output.

The waveforms in Fig. 8.32b illustrate the behavior.

VARIOUS REPRESENTATIONS Of fliP-flOPS

There are various ways a flip-flop can be represented, each one suitable for certain
application. Considering basic flip-flop truth table as starting point, this section derives
these representations.
Characteristic Equations of Flip-flops

The characteristic equations of flip-flops are useful in analyzing

circuits made of them. Here, next output Qn+1 is expressed as a
function of present output Qn and input to flip-flops
Flip-Flops as Finite State Machine

In a sequential logic circuit the value of all the memory elements

at a given time define the state of that circuit at that time.

Finite State Machine (FSM) concept offers a better alternative to

truth table in understanding progress of sequential logic with
time.

For a complex circuit a truth table is difficult to read as its size

becomes too large. In FSM, functional behavior of the circuit is
explained using finite number of states
Flip-Flop Excitation Table

In synthesis or design problem excitation tables are very useful

and its importance is analogous to that of truth table in analysis
problem. Excitation table of a flip-flop is looking at its truth table
in a reverse way.

This is derived from flip-flop truth table or characteristic

equation but more directly from its state transition diagram.
ANALYSIS Of SEQUENTIAL CIRCUITS
ANALYSIS Of SEQUENTIAL CIRCUITS
ANALYSIS Of SEQUENTIAL CIRCUITS
ANALYSIS Of SEQUENTIAL CIRCUITS
ANALYSIS Of SEQUENTIAL CIRCUITS
ANALYSIS Of SEQUENTIAL CIRCUITS
Explain the function of the circuit shown in Fig. 8.40 through
state transition diagram.
Solution
Convert an SR flip-flop to a JK flip-flop
Show how a D flip-flop can be converted to SR flip-flop.
HDLIMPlEMENTATION Of fllP-fLOP