Week 5 Memory
Week 5 Memory
MEMORY
Doan Duy, Ph. D.
Email: [email protected]
Overview of memory
Memory Organization
Example
Overview of memory
Memory Organization
Example
In embedded systems:
Communication with Sensors and Actuators
Often much more constrained than in general-purpose
computing: Size, power, reliability, etc.
Memory Map of an
ARM CortexTM - M3
architecture
Defines the mapping of
addresses to physical
memory.
Overview of memory
Memory Organization
Example
Statically-allocated memory
• Compiler chooses the address at which to store a
variable.
Stack
• Dynamically allocated memory with a Last-in,
First-out (LIFO) strategy
Heap
• Dynamically allocated memory
void foo(void) {
char *x, y;
x = &y;
*x = 0x20;
…
}
16 bits for x and 8 bits for y are allocated on the stack, then x is
loaded with the address of y, and then y is loaded with the 8-bit
quantity 0x20.
09/27/2024 Copyrights 2020 CE-UIT. All Rights Reserved. 14
Memory allocation (6)
What goes into z in the following program:
char foo() {
char y;
uint16_t x;
x = 0x20;
y = *x; z is loaded with the 8-bit
return y; quantity in the I/O register at
} location 0x20.
char z;
int main(void) {
z = foo();
…
}
Cache:
A subset of memory addresses is mapped to SRAM
Accessing an address not in SRAM results in cache miss
A miss is handled by copying contents of DRAM to SRAM
Scratchpad:
SRAM and DRAM occupy disjoint regions of memory space
Software manages what is stored where
Segmentation
Logical addresses are mapped to a subset of physical addresses
Permissions regulate which tasks can access which memory
Memory-
mapped I/O
devices
CPU
Cache Main memory Disk or Flash
registers
Memory-
mapped I/O
devices
Here, each distinct piece
CPU of memory hardware has
scratch
pad
its own segment of the
registers address space.
SRAM
This requires more
Main
memory careful software design,
register address
fits within one DRAM
but gives more direct
instruction word control over timing.
Disk or Flash
Overview of memory
Memory Organization
Example
ADC
Timer
0x83C00000
Subsystem Unmapped Area
0x8180FFFF
Interrupt controller
TIMER 0x81800000
Interrupt 0x0000FFFF
controller Memory for
Instructions and Data 0x00000000
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Copyrights 2020 CE-UIT. All Rights Reserved.
Conclusion