Homogeneous and

Heterogeneous Multi-
core Architectures
 Homogeneous and
Heterogeneous Multi-core
Architectures
• Multiprocessor systems contain multiple CPUs that are not on the same chip.
• Multi-core is a design in which single physical processor contains the core logic of more
than one processor.

• These processors are called cores. When these cores are integrated onto a single
integrated circuit die then they are known as a Chip multiprocessor or CMP or Dual core ,
• if these cores are built onto multiple dies in a single chip package

10/17/2024 2
Homogenous Multi-core architecture
• A Symmetric or Homogenous multi-core is one that has multiple cores on a single chip,
and all those cores are identical. Like AMP, an SMP system has multiple CPUs,

• but in this case each has exactly the same architecture – i.e. it must be a homogeneous
multi-core design.

• CPUs share memory space (or at least some of it).

10/17/2024 3
• Normally a single OS is used that runs on all the CPUs, dividing work between them -
another significant difference from AMP.
• Some kind of communication facility between the CPUs is provided this is normally
through shared memory,
• but accessed through the API of the OS. Typically, SMP is used when an embedded
application
• simply needs more CPU power to manage its workload, in much the way that multicore
CPUs are used in desktop computers.

10/17/2024 4
10/17/2024 5
• The Intel core 2 is an example of a symmetric multi-core processor.

• The core 2 can have either 2 cores on chip (―Core2 Duo‖) or 4 cores on chip (―Core 2
Quad‖).
• Each core in core 2 chip is symmetrical and can function independent of one another.

• It requires a mixture of scheduling software and hardware to form tasks out to each core.

10/17/2024 6
• Every Single core has the same architecture and same capabilities.

• Each core has the same capabilities so it requires that there is an arbitration unit to give
each core a specific task.

• Software that uses techniques like multithreading makes the best use of multi-core
processor like the Intel core 2

10/17/2024 7
Heterogeneous Multi-core
architecture
• An asymmetric multi-core processor is one that has multiple cores on
a single chip, but those cores might be different designs.

• For instance, there could be 2 general purpose cores and 2 vector

cores on a single chip.

10/17/2024 8
• The best example of heterogeneous multi-core is the cell processor which is a
heterogeneous multi-core processor comprised of control intensive processor and
compute intensive SIMD processor cores,

• each with its own distinguishing features. In an asymmetric multi-core processor, the
chip has multiple cores on board, but the cores might be different designs. Each core will
have different capabilities

10/17/2024 9
10/17/2024 10
• The figure above shows the structural layout of a configuration of heterogeneous
multi-core processor. In this,
• the core A differs from all other common cores (core B) which mean that all the
cores within the same processor are not symmetric.
• Hence heterogeneous processor is also called Asymmetrical multi-core processor.

10/17/2024 11
• Heterogeneous system improve performance and efficiency by exposing to programmers
architectural features,

• such as low latency software-controlled memories and inter-processor interconnect, that

are either hidden or unavailable in GPPs.
•
• The software that executes on these accelerators often bears little resemblance to its
CPU counterpart

10/17/2024 12
• Heterogeneous systems integrate computational resources that features instruction sets
and functionality that significantly differ from general-purpose processors(GPPs). These
systems fall
• into two categories:
• 1. an ISA-based tightly-coupled model
• 2. a device driver based loosely-coupled execution model
• HMT: Hardware Multithreading. There are many threads per core.
• CMT: Chip Multithreading has support to CMP Technology and HMT Technology

10/17/2024 13
components
• The primary core would be generic processor for running basic programs.
•  A graphics core to handle all graphics and display algorithms
•  A protocol offload engine – POE which acts as a communication processor core that will
handle all communication tasks.
•  A math-oriented processor core to handle all the heavy calculations that some of the
applications programs may have.

10/17/2024 14
10/17/2024 15
MULTICORE
• SHARED MEMORY

10/17/2024 16
Introduction:Multiproce
ssors
Characteristics of Multiprocessors
•Multiprocessors System = MIMD
• An interconnection of two or more CPUs with memory and I/O equipment
• a single CPU and one or more IOPs is usually not included in a multiprocessor system
• Unless the IOP has computational facilities comparable to a CPU
•Computation can proceed in parallel in one of two ways
• 1) Multiple independent jobs can be made to operate in parallel
• 2) A single job can be partitioned into multiple parallel tasks
•Classified by the memory Organization
• 1) Shared memory or Tightly-coupled system: Provides a cache memory with each CPU and
there is Global common memory that all CPU can access.
• Local memory + Shared memory
• 2) Distribute memory or Loosely-coupled system
• Local memory + message passing scheme (I.e. the processors are tied together by a
switching scheme designed to route information from one processor to another though
message passing scheme.
•Interconnection Structure: the components that form the multiprocessor system are CPU ,IOP
connected to I/O devices , and memory unit that may be portioned into a number of separate
modules.
• Multiprocessor System Components
• 1) Time-shared common bus
• 2) Multi-port memory
• 3) Crossbar switch
• 4) Multistage switching network
• Time-shared Common Bus
• Time-shared single common bus system :
• Only one processor can communicate with the memory or another processor at any
given time
• when one processor is communicating with the memory, all other processors are either busy
with internal operations or must be idle waiting for the bus

Memory unit

CPU 1 CPU 2 CPU 3 IOP 1 IOP 2

 Dual common bus system :
Tightly coupled system
»System bus + Local bus
»Shared memory
 the memory connected to the common system bus is shared by
all processors

»System bus controller

 Link each local but to a common system bus

Local bus

COmmon System
Local
shared bus CPU IOP
memory
memory controller

System Bus

System System
Local Local
bus CPU IOP bus CPU
memory memory
controller controller

Local bus Local bus

• Multi-port memory :
• multiple paths between processors and memory
• Advantage : high transfer rate can be achieved
• Disadvantage : expensive memory control logic / large number of cables &
connectors Memory modules

MM 1 MM 2 MM 3 MM 4

CPU 1

CPU 2

CPU 3

CPU 4
Crossbar Switch :
Crosspoints
are placed at intersections between processor buses and
memory module paths.
A small square in each crosspoints is a switch that determines the path from
a processor to a memory module.
Each switch point has a control logic to set up the transfer path between
processor and memory module. CPUs
Memory modules MM
MM 1 MM 2 MM 3 MM 4

Data,address, and
control form CPU 1

Data
CPU 1

Data,address, and
Addres Multiplexer control form CPU 2
s s and
Memory
CPU 2
module arbitration
Read/ logic
write Data,address, and
control form CPU 3
CPU 3 Memor
y
enabl
e Data,address, and
control form CPU 4
CPU 4
• Multistage Switching Network
• Control the communication between a number of sources and
destinations
• Tightly coupled system : PU MM
• Loosely coupled system : PU PU
• Basic components of a multistage switching network are
two-input, two-output interchange switch : the two Input has labled A
& B and two output labeled 0 & 1.
0 0
A A
1 1
B B

A connected to 0 A connected to 1

0 0
A A
1 1
B B

B connected to 0 B connected to 1
 0
Itis possible to build a 000
1
multistage network to 0
001

control the 1
communication between 0
010

number of sources and 1

011
0
destinations. P0
1
P1
The 2 Processor (P1 and 0
100

P2) are connected 1

101
0
through switches to 8
memory modules 1
0
110
marked by (000 - 111) 1
111
Omega Network : 2 x 2 Interchange switch with N input x N output
network topology

0 000

1 001

2 010

3 011

4 100

5 101

6 110

7 111
• Hypercube Interconnection :
• The hypercube or binary n-cube multiprocessor structure is a Loosely coupled
system composed of N=2n processors interconnected in an n-dimensional binary
cube. Each processor forms a node for the cube.
• Hypercube Architecture : Intel iPSC ( n = 7, 128 node )

0 11 111

0 01 11 010 11 0

001 101

0 00 10 000 100